Stacked Redistribution Layers for PCB-Free Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high electrical performance and structural stability while minimizing size and manufacturing costs, particularly in integrating multiple components into a single package without additional printed circuit boards.
Innovation Solution
The semiconductor device design includes a first semiconductor chip with a redistribution layer, a second semiconductor chip stacked vertically with its own redistribution layer, and a mold layer extending on the sidewalls, with external terminals electrically connected through a connection wire, allowing for efficient electrical connection and miniaturization without requiring additional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are integrated in a single package without additional PCB, then device size is reduced and manufacturing cost is lowered, but electrical performance and structural stability deteriorate
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking, placing semiconductor chips at different vertical levels and connecting them through redistribution layers and connection structures that extend in the vertical dimension, thereby achieving high-density integration while maintaining electrical performance
Solution Approach 2:
The patent implements a nested structure where semiconductor chips, redistribution layers, and connection structures are integrated within a single package housing, with each component contained within and supporting the next level of the hierarchy, eliminating the need for external PCB connections
2Volume of moving object
If multiple semiconductor chips are integrated in a single package without additional PCB, then device size is reduced, but structural stability deteriorates
Solution Approach 1:
The patent employs composite packaging structures that combine multiple materials with complementary properties, including rigid support structures for structural stability and flexible connection structures for electrical connectivity, creating a unified package that maintains both mechanical strength and electrical performance
Solution Approach 2:
The patent uses vertical stacking and three-dimensional arrangement of chips and connection structures, providing structural support through the vertical dimension while reducing the horizontal footprint, thereby maintaining structural stability in a compact form factor
3Reliability
If complex redistribution processes are used to connect chips in wafer-level package, then electrical connection is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent performs preliminary formation of redistribution layers and connection structures during the chip fabrication process itself, rather than adding them afterward through complex post-processing steps, thereby simplifying the overall manufacturing workflow while ensuring reliable electrical connections
Solution Approach 2:
The patent combines multiple functions into integrated structures, where redistribution layers serve both as electrical interconnects and as structural support elements, reducing the number of separate manufacturing steps and components needed while maintaining electrical performance
Data Source
AI summary
Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.