PCB Capacitor Ground Via Layout for Power Supply Noise Isolation

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Solution Overview

Problem

Existing electronic modules face challenges in reducing power supply noise propagation between semiconductor circuits due to common ground connections, leading to unstable operation, especially when circuits with different power supply current levels are involved.

Innovation Solution

The electronic module incorporates a printed wiring board with capacitors mounted on opposite surfaces, where the capacitors' electrodes are connected to power supply and ground lines, and a ground pattern is used to increase impedance, preventing noise propagation by creating a longer conduction path and reducing high-frequency noise transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If multiple bypass capacitors are connected to a common ground, then power supply noise is reduced, but noise propagates between circuits through the ground

Engineering Contradiction:
Improvepower supply noiseVSAvoidcircuit operation stability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The ground connection is segmented into multiple separate ground vias (first ground via, second ground via) that connect to different ground patterns. This segmentation prevents noise from propagating between circuits through a common ground path, while still maintaining effective noise reduction for each individual circuit through its dedicated capacitor-ground connection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each capacitor is provided with separate ground connections (first ground via for first capacitor, second ground via for second capacitor) tailored to their respective circuits. This local differentiation ensures that noise reduction is optimized for each circuit without causing cross-contamination, as each circuit has its own dedicated ground path.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If capacitors are mounted on the back surface of the printed wiring board, then power supply noise is reduced, but the ground connection path becomes longer

Engineering Contradiction:
Improvepower supply noiseVSAvoidground conduction path
Core Design Contradiction:
Object-affected harmful factorsVSLength of stationary object

Solution Approach 1:

The ground connection transitions from a two-dimensional surface trace to a three-dimensional path using vertical vias through the insulating board. This dimensional change allows the ground connection to be made shorter and more direct by utilizing the thickness dimension of the board, reducing the overall ground path length despite the capacitors being mounted on the back surface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces power supply noise from propagating between circuits, ensuring stable operation by controlling impedance and minimizing noise transmission, particularly in high-density wiring environments.

Implementation Method 1

The ground line includes a first ground via, a second ground via, and a ground pattern formed in the insulating board. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via. The fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via.

Methodology Applied
Scientific EffectElectrical Impedance: Electrical Resistance

Data Source

PatentUS11792917B2Electronic module and electronic apparatus
Publication Date: 2023.10.17 CANON KK
  • US11792917B2 patent drawing
  • US11792917B2 patent drawing
  • US11792917B2 patent drawing

AI summary

An electronic module includes a first semiconductor device disposed on a first main surface of an insulating board of a printed wiring board, a first capacitor disposed on a second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in the direction perpendicular to the first main surface. A second electrode of the first capacitor is electrically connected to a ground pattern via a first ground via of the printed wiring board. A fourth electrode of the second capacitor is electrically connected to the ground pattern via a second ground via of the printed wiring board.