PCB High-Potential Testing via Adjacent Land Pair Selection
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Solution Overview
Problem
Current high-potential testing of printed circuit boards is time-consuming and inefficient, as it typically requires testing all possible combinations of conductive land pairs, which can lead to inadequate testing of complex designs and prolonged fabrication times.
Innovation Solution
A method that identifies and tests only adjacent conductive land pairs using a test pattern generator and adjacency assessment, reducing the number of test combinations and improving efficiency by selectively targeting electrically adjacent conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all possible combinations of conductive land pairs are tested, then testing completeness is improved, but test time increases significantly
Solution Approach 1:
The patent extracts and identifies only the adjacent conductive land pairs from the complete set of all possible conductive land pairs. By using adjacency assessment, the method separates the critical subset of pairs that require testing from the non-critical pairs, thereby reducing the test scope while maintaining testing effectiveness for dielectric breakdown detection.
Solution Approach 2:
The patent applies local quality by focusing testing resources on specific locations where dielectric breakdown is most likely to occur - namely, adjacent conductive land pairs. Instead of uniform testing across all pairs, the method concentrates test efforts on locally critical areas identified through adjacency assessment, optimizing the balance between testing completeness and time efficiency.
2Reliability
If high-potential testing is performed on all conductive land pairs, then dielectric integrity is thoroughly verified, but fabrication throughput decreases
Solution Approach 1:
The patent extracts the essential subset of adjacent conductive land pairs that represent the critical test cases for dielectric integrity. By identifying and testing only these adjacent pairs through systematic adjacency assessment, the method verifies dielectric integrity where it matters most while eliminating redundant tests on non-adjacent pairs, thus maintaining reliability while improving fabrication throughput.
3Reliability
If complex PCB designs with thousands of conductive shapes are fully tested, then testing coverage is maximized, but test feasibility is compromised
Solution Approach 1:
The patent extracts a manageable subset of adjacent conductive land pairs from the thousands of possible pairs in complex PCB designs. By using adjacency assessment to identify only the critical pairs, the method makes testing feasible for complex designs while maintaining adequate coverage of dielectric integrity concerns, transforming an intractable full-testing problem into a practical solution.
Solution Approach 2:
The patent applies local quality by concentrating testing on adjacent conductive land pairs where dielectric breakdown is most probable. This localized approach to complex PCB designs with thousands of conductors makes testing feasible by reducing the problem size while maintaining effectiveness in the critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces high-potential test time and improves fabrication throughput by focusing on adjacent conductive land pairs, allowing for practical and efficient high-potential testing of printed circuit boards.
Implementation Method 1
An electric field is related to voltage through the following equation. E=−∇V. If the intensity of the electric field is too strong, the dielectric will breakdown and no longer insulate conductors.
Data Source
AI summary
A method for testing a printed circuit board is provided. The method includes accessing a list of conductive lands of a printed circuit board to be tested and forming a list of pairs of adjacent conductive lands, based on adjacency assessment in the list of conductive lands. The method includes performing high-potential testing on the printed circuit board, on each of the pairs of adjacent conductive lands.