PCB Interconnect Structure for High Density Power Contactor
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Solution Overview
Problem
The existing printed wiring boards for aerospace applications require a large amount of space due to the co-planar positioning of input and output buses, which increases the overall size and reduces component density, as MOSFETs are connected by wires, leading to inefficient space utilization and thermal management.
Innovation Solution
The printed circuit board design positions the transistor intermediate to the input and output buses in a non-co-planar manner, with direct solder interconnects allowing for reduced spacing between bus bars, increasing density and reducing heat load by allowing more bus bars to be packaged in a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If input and output buses are positioned in a common plane with wire connections, then electrical connectivity is achieved, but the overall size becomes undesirably large
Solution Approach 1:
The patent transitions from a two-dimensional coplanar bus arrangement to a three-dimensional stacked configuration where input and output buses are positioned on different layers. This vertical stacking eliminates the need for lateral wire connections, reducing the overall footprint while maintaining electrical connectivity through direct vertical interconnects.
Solution Approach 2:
The patent integrates the transistor structure directly between the input and output buses in a stacked configuration, merging previously separate components (buses, transistors, and wire connections) into a compact unified structure. This consolidation eliminates the need for external wire connections and reduces overall device volume.
2Area of moving object
If MOSFETs are connected by wires between coplanar buses, then electrical connectivity is achieved, but space between fingers becomes excessively large
Solution Approach 1:
The patent moves from a planar two-dimensional layout to a three-dimensional stacked architecture where input and output buses are separated in the vertical dimension rather than spaced laterally. This allows finger structures to be positioned closer together in the horizontal plane while maintaining adequate electrical spacing vertically, thereby increasing component density.
Solution Approach 2:
The patent implements a nested structure where the transistor is positioned between and connected to the input and output buses in a compact stacked arrangement. This nesting of components in the vertical dimension allows for tighter horizontal spacing of bus fingers while maintaining proper electrical connections.
3Temperature
If coplanar bus configuration is used, then manufacturing is simpler, but thermal management becomes inefficient
Solution Approach 1:
The patent utilizes vertical stacking to create separated thermal zones for input and output buses on different layers. This three-dimensional arrangement improves thermal management by allowing independent thermal paths and heat dissipation for each bus, preventing heat accumulation that would occur in coplanar configurations where buses are in direct thermal contact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the overall size of the printed wiring board by 33% and improves thermal management by enabling a higher current flow per bus bar compared to prior art, while maintaining efficient power communication.
Implementation Method 1
direct solder interconnects allowing for reduced spacing between bus bars
Data Source
Figure 1
Figure 2
AI summary
A printed circuit board (21) for selectively communicating power from a power source to a use has an input bus (24) for receiving a power supply (22). A transistor (26) is connected to the input bus (24) and is positioned on one side of the input bus (24) in a first direction. An output bus (34) is connected to the transistor (26) on an opposed side of the transistor (26) relative to the input bus (24). The transistor (26) is intermediate at the first input and output buses (24, 34) in the first direction (X). A power supply system (20) is also disclosed.