PCB Layout for Mitigating Near-End Crosstalk
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Solution Overview
Problem
Increasing trace density on printed circuit boards (PCBs) in information handling systems leads to crosstalk issues, degrading signal integrity and increasing bit error rates, which conventional design rules attempt to mitigate by spacing traces far apart, but this increases costs and complexity.
Innovation Solution
Implementing design rules that allow traces to be spaced closer together by setting the ratio of core height to prepreg height approximately equal to one, and the trace spacing distance to core height distance less than five times the prepreg height, reducing crosstalk and enabling higher trace density without adding layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trace density is increased to accommodate more components and data rates, then productivity and functionality are improved, but crosstalk increases degrading signal integrity
Solution Approach 1:
The patent changes the geometric parameters of the PCB structure by setting the ratio of core height to prepreg height approximately equal to one, and positioning traces such that the ratio of trace spacing distance to core height is less than five times the prepreg height. These parameter changes optimize the electromagnetic field distribution and reduce crosstalk, enabling higher trace density while maintaining signal integrity.
2Reliability
If conventional design rules are followed to minimize crosstalk by spacing traces far apart, then signal integrity is maintained, but trace density decreases increasing device complexity and cost
Solution Approach 1:
The patent modifies the conventional design parameters by optimizing the core height to prepreg height ratio to approximately one, and adjusting trace spacing to achieve a trace spacing distance to core height ratio of less than five times the prepreg height. These parameter changes enable reduced trace spacing while maintaining signal integrity, avoiding the need to add PCB layers.
3Area of stationary object
If trace spacing is reduced to increase trace density, then area utilization is improved, but crosstalk increases causing bit errors
Solution Approach 1:
The patent optimizes the geometric parameters by setting the core height to prepreg height ratio approximately equal to one, and positioning traces to achieve a trace spacing distance to core height ratio of less than five times the prepreg height. These parameter changes create an electromagnetic environment that reduces crosstalk even at reduced trace spacing, enabling higher area utilization.
4Reliability
If more PCB layers are added to space traces vertically, then crosstalk is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the vertical stacking parameters by optimizing the core height to prepreg height ratio to approximately one, which creates favorable electromagnetic shielding and field distribution within the existing PCB layers. This parameter optimization reduces crosstalk without requiring additional PCB layers, simplifying manufacturing.
Data Source
AI summary
Traces on a PCB can be spaced closer together than in conventional layouts, which previously required the pair-to-pair spacing for the high-speed differential stripline signals to be at least 5H if the signals are originating from the same source and 7H when the signals on two pairs of transmission lines in the traces originate from different sources. Traces may be spaced closer together when, for example, a ratio of the core height to the prepreg height of the printed circuit board is approximately equal to one. Traces may be spaced closer together when, for example, a ratio of the trace spacing distance to the core height distance is less than approximately one. By implementing one or both of these design rules, printed circuit board layouts can be designed, and printed circuit boards manufactured from those designs, that have an intra-group spacing between the first pair and the second pair measured at a point at which the first pair is closest to the second pair of less than approximately five times the prepreg height (the limit for previous printed circuit board designs).