PCB Layout Method for High-Speed Memory Bus Design
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Solution Overview
Problem
The miniaturization of printed circuit boards (PCBs) and increasing signal frequencies pose challenges in designing efficient high-speed memory bus layouts, requiring advanced methods to simplify component placement and routing configurations.
Innovation Solution
A layout method for PCBs that involves obtaining specific routing modules from a database based on PCB parameters and memory types, incorporating layout information for main and memory chips, and implementing these modules into the design using electronic design automation tools, thereby simplifying the design of high-speed memory buses and reducing design time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If PCB size is miniaturized to meet product size requirements, then product compactness is improved, but layout design complexity increases
Solution Approach 1:
The patent divides the PCB layout design into multiple modules, where each module contains pre-defined routing configurations for specific memory types and chip arrangements. This modular approach allows designers to select and assemble predefined modules rather than creating entire layouts from scratch, thereby reducing design complexity despite PCB miniaturization.
Solution Approach 2:
The patent pre-defines routing modules with optimized trace patterns, via placements, and connection configurations for different memory types (e.g., LPDDR, DDR). These pre-configured modules are stored in a database and can be directly applied during design, eliminating the need for time-consuming manual routing optimization and reducing overall design complexity.
2Speed
If signal frequency is increased to improve product performance, then processing speed is improved, but routing design difficulty increases
Solution Approach 1:
The patent pre-optimizes routing modules for high-frequency signal transmission by incorporating impedance-controlled trace designs, proper via configurations, and signal integrity considerations into the module templates. When a designer selects a routing module for high-speed memory (e.g., LPDDR4, DDR5), the module already contains frequency-optimized routing patterns, eliminating the need for complex manual high-frequency routing design.
3Reliability
If manual layout design is used to ensure signal performance, then signal quality is improved, but design time increases
Solution Approach 1:
The patent segments the layout design into reusable modules that encapsulate signal integrity optimizations. Each module is pre-designed and verified for proper signal performance, allowing designers to maintain high signal quality by selecting appropriate modules while significantly reducing the time required for manual routing and optimization.
Solution Approach 2:
The patent performs signal integrity optimization in advance during module creation, including trace impedance control, via stitching patterns, and reference plane configurations. These pre-optimized modules can be directly applied without requiring extensive manual tuning, thus maintaining signal performance while reducing design time.
4Reliability
If routing configurations are customized for each design to optimize performance, then signal integrity is improved, but design costs increase
Solution Approach 1:
The patent creates universal routing modules that can be applied across multiple different PCB designs and memory configurations. A single routing module may support various memory types (LPDDR, DDR) and can be adapted to different chip placements through parameterization, eliminating the need to create custom routing for every design while maintaining signal integrity.
Solution Approach 2:
The patent divides routing designs into standardized modules that can be reused across different projects. By segmenting the routing into modular units with defined interfaces and connection points, the same modules can be applied to multiple designs with minimal modification, reducing overall design costs while preserving signal integrity through proven routing patterns.
Data Source
AI summary
A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.