PCB Layout Parasitic Impedance Estimation via Machine Learning
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Solution Overview
Problem
Current circuit board layout tools inaccurately predict parasitic impedances, leading to performance discrepancies between simulation and measurement, which prolongs the design cycle and increases manufacturing costs due to iterative revisions.
Innovation Solution
The implementation of a machine learning system, specifically a graphical neural network (GNN), that analyzes PCB layouts to estimate parasitic impedances more accurately, allowing for better prediction of circuit board performance before manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current circuit board layout tools are used to estimate parasitic impedances, then the design process is simple and fast, but the prediction accuracy of parasitic impedances is insufficient
Solution Approach 1:
The patent introduces machine learning models as an intermediary between the PCB layout and parasitic impedance estimation. The machine learning model is trained on simulation data to serve as a mediator that translates layout features into accurate parasitic impedance predictions, resolving the contradiction between simplicity and accuracy.
Solution Approach 2:
The patent applies preliminary action by pre-training machine learning models using electromagnetic simulation data before actual PCB design work. This pre-computation of training data from detailed simulations allows the model to learn accurate parasitic impedance relationships in advance, providing fast and accurate predictions during subsequent design iterations without requiring repeated full simulations.
2Measurement precision
If iterative PCB designs are manufactured to improve performance accuracy, then the prediction accuracy improves, but the time and cost increase
Solution Approach 1:
The patent creates a virtual copy of the complex electromagnetic simulation process through machine learning models. Instead of repeatedly manufacturing physical PCBs for testing, the trained model serves as a virtual replica that can quickly predict performance outcomes for different layout iterations, eliminating the need for multiple physical prototypes and reducing design cycle time.
Solution Approach 2:
The patent replaces the mechanical/physical iteration process of manufacturing and testing PCBs with a computational machine learning system. The machine learning model substitutes the physical trial-and-error process, providing fast virtual predictions that eliminate the time-consuming cycle of manufacturing multiple PCB revisions for performance validation.
3Measurement precision
If machine learning models are trained with simulation data, then the prediction accuracy improves, but the training time and computational resources increase
Solution Approach 1:
The patent applies preliminary action by performing the computationally intensive simulation work once during the data preparation phase to create training datasets. This upfront investment in generating training data from simulations enables the machine learning model to learn accurate relationships, after which the model provides fast predictions without requiring repeated full simulations for each design iteration.
Data Source
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AI summary
This disclosure is directed to a system and method for applying machine learning model (300) to a PCB layout (310) to obtain an estimate of the parasitic values of the board (320). The machine learning model (300) may be trained with various PCB layouts (310) to accurately determine an estimated parasitic impedance (329). Determine regions of the board having a high parasitic impedance value, alerting the user to reconfiguring the region so to achieve a desired range of values.