PCB-Mounted Equivalent Load Module for Transient IC Testing
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Solution Overview
Problem
Existing electronic load testing systems face challenges in tightly packed systems due to form factor limitations and inductive connections, particularly when testing complex PCBs with multiple processors and ICs, which require precise power management and transient current handling.
Innovation Solution
A form factor equivalent load testing device (FFED) is designed to be directly mounted on the PCB, using existing traces for communication between control and load modules, mimicking the IC's dimensions and thermal properties, and employing load cells with fast switching capabilities to simulate current and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the power load portion is separated from the control circuitry to reduce form factor, then the form factor is improved and current capacity is increased, but a large multiconductor cable is required which becomes ungainly and difficult to implement in complex systems
Solution Approach 1:
The patent introduces a PCB trace as an intermediary connection medium between the power load portion and control circuitry. Instead of using a large multiconductor cable directly, the invention utilizes existing PCB traces to make the necessary electrical connections, thereby eliminating the ungainly cable while maintaining the separated architecture benefits.
Solution Approach 2:
The invention copies the connection methodology from integrated circuit interconnections to the load testing system. By using PCB traces similar to those found in ICs, the system replicates the compact connection approach, avoiding the need for external cables and achieving IC-like integration density.
2Quantity of substance
If a large-gauge cable or ribbon cable is used to connect external load, then current capacity is improved, but inductance increases making such connections too inductive to allow slew rates exceeding 1000 A/us
Solution Approach 1:
The patent replaces the mechanical cable connection system with an electrical trace-based system. By substituting physical cables with PCB traces, the invention eliminates the inductance problem inherent in cable connections while maintaining the ability to handle high current capacities required for processor testing.
Solution Approach 2:
The invention changes the connection medium's electrical parameters by using PCB traces with controlled impedance and minimal inductance. This parameter change allows the system to achieve the required slew rates exceeding 1000 A/us while maintaining adequate current capacity, fundamentally altering the electrical characteristics of the connection path.
3Device complexity
If control circuitry is fitted in the same assembly as the power load portion, then overall complexity is reduced, but form factor increases presenting challenges in tightly packed systems
Solution Approach 1:
The patent divides the load testing system into separate functional modules: a power load portion and a control circuitry portion. This segmentation allows each module to be optimized independently for its specific function while maintaining a compact overall form factor suitable for tightly packed systems.
Solution Approach 2:
The invention resolves the complexity-form factor tradeoff by transitioning from a vertically stacked integrated design to a distributed layout utilizing PCB trace routing. This dimensional change in the connection approach allows separation of functions while maintaining compact footprint through planar circuit board routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FFED provides accurate and realistic testing of power distribution and thermal management, ensuring compliance with IC specifications by simulating transient currents and thermal loads, thus optimizing the PCB's performance.
Implementation Method 1
the load cell comprising a transistor and a current sense resistor
Implementation Method 2
the load cell comprising a transistor and a current sense resistor
Data Source
AI summary
An electronic load testing system is configured to emulate aspects of an integrated circuit (IC). A control module of the system is configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic assembly, and a load module is configured to be electrically coupled to a second location on the PCB. The load module includes a load cell configured to selectively conduct current from a power supply of the electronic assembly. The first location and the second location are spaced apart and in electronic communication via one or more traces of the PCB. The control module is configured to communicate with the load module via the one or more traces of the PCB. In some examples, the load module and the IC have an equivalent form factor, such that the load module can be installed in place of the IC.