PCB Memory Chip Cable Routing for Signal Integrity
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Solution Overview
Problem
In DDR dual-rank memory systems, the long cable sections connected to one pin compromise signal integrity and require complex multilayered PCB designs, posing high technological challenges.
Innovation Solution
A storage apparatus with a conversion module, rank decision device, and switching array that connects two pins using one cable, ensuring extremely short cable sections and accurate signal transmission by converting system bus signals into rank selection and memory chip bus signals, and controlling signal output through single-pole double-throw switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a T-type cable design is used to connect same pins of two memory chips, then signal integrity of one pin is ensured through a short cable section, but signal integrity of the other pin deteriorates due to a long cable section
Solution Approach 1:
The patent segments the cable connection by introducing via holes that pass through the PCB, dividing the cable path into separate sections for each memory chip. This allows each memory chip to have its own optimized cable section length, ensuring signal integrity for both pins independently rather than having one long and one short section in a T-type design
Solution Approach 2:
The via holes act as intermediaries that facilitate the cable connection between the two memory chips. By using via holes as the connecting structure, the patent enables direct through-hole connections that balance the cable lengths for both pins, eliminating the signal integrity issue caused by asymmetric cable sections in T-type design
2Reliability
If multiple layers are designed in PCB to implement cables and prevent interference, then cable interference is avoided, but device complexity and technological requirements increase
Solution Approach 1:
The patent segments the cable routing by using via holes to create separate connection paths through different PCB layers. This segmentation allows cables to be routed independently without interference, achieving reliable signal transmission without requiring an excessively complex multilayered PCB structure
Solution Approach 2:
The patent transitions from planar cable routing to three-dimensional routing by utilizing via holes that pass through the PCB thickness direction. This dimensional change enables cables to cross layers without interfering with each other, preventing signal interference while maintaining a manageable PCB layer structure
Data Source
AI summary
A storage apparatus includes a printed circuit board (PCB) and multiple memory chips symmetrically arranged on two sides of the PCB, where multiple memory chips on one side of the PCB form a rank, and multiple memory chips on the other side of the PCB form a rank; a memory chip includes multiple pins; multiple cables are disposed in the PCB; and one cable of the multiple cables is connected to two pins in a same position on the two sides of the PCB.