PCB Over-Stress Analysis via Subcircuit Partitioning
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Solution Overview
Problem
Current methods are inadequate for simulating large and complex printed circuit boards (PCBs) due to the difficulty in estimating electrical over-stress, as they cannot accurately model and simulate the electrical conditions of thousands of components across multiple design fabrics, leading to incomplete stress analysis.
Innovation Solution
A computer-implemented method that splits an electronic design schematic into subcircuits, independently simulates each subcircuit, and analyzes the results to determine over-stress, using techniques such as bias nets, digital nets, and connectors as terminating interfaces, and pin information to apply stimuli, enabling the identification of overstressed devices within a graphical user interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the entire PCB circuit is simulated at once, then complete system-level electrical stress analysis can be obtained, but the simulation becomes computationally infeasible due to the large number of components and complexity of the circuit
Solution Approach 1:
The patent divides the large PCB circuit into multiple smaller subcircuits based on functional modules or component groups. Each subcircuit is simulated independently to calculate electrical stress parameters, and the results are then aggregated to obtain the overall system-level electrical stress analysis. This segmentation makes the simulation computationally feasible while maintaining analysis completeness.
2Productivity
If the PCB circuit is divided into subcircuits for independent simulation, then computational feasibility is improved, but the accuracy of system-level electrical stress analysis may be compromised due to ignoring interactions between subcircuits
Solution Approach 1:
The patent implements an iterative simulation process where initial subcircuit simulations are performed, results are analyzed, and feedback is used to adjust simulation parameters or refine subcircuit boundaries. This feedback mechanism ensures that interaction effects between subcircuits are captured in subsequent iterations, improving the accuracy of the overall electrical stress analysis while maintaining computational efficiency.
3Measurement precision
If manual circuit simulation methods are used, then detailed analysis can be performed, but the process becomes extremely time-consuming and labor-intensive for large PCB designs
Solution Approach 1:
The patent implements automated subcircuit identification and partitioning algorithms that automatically analyze the PCB netlist, identify functional modules, and divide the circuit into appropriate subcircuits without manual intervention. The system also automatically aggregates simulation results from subcircuits to produce comprehensive system-level electrical stress reports, eliminating manual compilation time while maintaining detailed analysis capability.
Data Source
AI summary
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to determine over-stress associated with the plurality of subcircuits.