Nickel-Gold Plating on PCB Pads via Through-Hole Alignment
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Solution Overview
Problem
The existing non-plating line (NPL) process for fabricating circuit boards with nickel/gold layers is complex and prone to alignment errors, leading to incomplete electroplating on fine-pitch electrically connecting pads, which increases fabrication time and cost.
Innovation Solution
A method involving the formation of through holes in a circuit board with conductive structures, where a conductive layer connects electrically connecting pads on both sides, allowing for electroplating of a metal protecting layer through a simplified photoresist image transfer process, reducing the need for conductive films on both surfaces and aligning resist layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-plating line (NPL) process is used to electroplate nickel/gold layers on connecting pads, then oxidation prevention and electrical connection quality are improved, but the fabrication process becomes complicated and the process cycle is prolonged
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming conductive films on specific surfaces, creating resist patterns, electroplating metal layers, and removing resist. This segmentation allows each step to be optimized independently, simplifying the overall process while maintaining reliability.
Solution Approach 2:
The patent applies preliminary actions by pre-forming conductive films on the circuit board surfaces before the electroplating process. This preparation ensures that the electroplating can proceed efficiently with proper adhesion, reducing process complexity and cycle time.
2Manufacturing precision
If photoresist image transfer process is performed twice on top and bottom surfaces with fine pitch ball pads, then alignment precision is improved, but the process cycle is prolonged and alignment errors still occur
Solution Approach 1:
The patent merges the photoresist image transfer operations into a single process step by using a through-hole structure that allows the resist pattern to be formed once and used for both top and bottom surface alignment. This eliminates the need for separate resist application and alignment steps on each surface, reducing cycle time while maintaining precision.
Solution Approach 2:
The patent introduces a through-hole dimension that penetrates the circuit board, allowing the resist pattern to be formed in one location and serve alignment purposes for both top and bottom surfaces. This dimensional approach eliminates the need for repeated 2D alignment operations.
3Reliability
If conductive films are formed on both top and bottom surfaces with multiple resist layers, then complete electroplating coverage is achieved, but the fabrication process becomes more complex
Solution Approach 1:
The patent extracts the unnecessary conductive films and resist layers from the process by using a through-hole structure that allows single-sided resist application to control electroplating on both surfaces. This extraction simplifies the material stack while maintaining complete electroplating coverage where needed.
Solution Approach 2:
The through-hole structure acts as an intermediary that transmits the resist pattern from one surface to the other, enabling single-sided resist application to control electroplating on both top and bottom surfaces. This intermediary eliminates the need for multiple resist layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process, reduces cycle time, and effectively forms metal protecting layers on fine-pitch electrically connecting pads, meeting the requirements of compact electronic products by eliminating alignment errors and reducing exposure process time.
Implementation Method 1
forming at least one conductive layer on the first circuit layer, so as to electrically connect the electrically connecting pads of the first and second circuit layers
Implementation Method 2
electroplating the metal protecting layer on the electrically connecting pads of the first and second circuit layers through the conductive layer
Data Source
AI summary
This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a portion of the conductive film in an electrically connecting pad area intended for the circuit layer; removing a portion of the conductive film not covered with the resist; forming another resist on the substrate to cover a portion of the conductive film residually exposing from the resist; electroplating nickel/gold on at least one electrically connecting pad on the substrate such that the electrically connecting pad is electroplated with a nickel/gold layer; removing the resists and the conductive film thereunder; and forming a solder mask on the substrate, wherein the electrically connecting pad electroplated with the nickel/gold layer is exposed from the solder mask. The structure comprises a substrate circuit-patterned and defined with a circuit layer, wherein the circuit layer is provided with at least one electrically connecting pad exposed from a resist, the exposed surface of the electrically connecting pad is electroplated with a nickel/gold layer, and the substrate is spared with an electroplating wire for electroplating nickel/gold on the electrically connecting pad.