PCB Passive Elements Counteract Parasitic Signal Distortion

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Solution Overview

Problem

Current printed circuit boards suffer from signal distortion due to parasitic effects like parasitic capacitance and inductance, which are challenging to mitigate without increasing design and manufacturing costs or altering physical topology, especially when parasitic effects dominate.

Innovation Solution

Incorporating passive elements adjacent to the conductive pathways without connecting to them, which provide corrective effects such as inductance or capacitance to counteract parasitic effects, thereby reducing signal distortion. These passive elements can be implemented as traces, microstrips, or combinations with inductors or capacitors to optimize signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional solutions like shorter trace length, back filling, buried vias, or blind vias are used to reduce parasitic effects, then signal distortion is reduced, but design and manufacturing costs increase

Engineering Contradiction:
Improvesignal integrityVSAvoiddesign and manufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent introduces an intermediary component (the fourth via) that acts as a mediator to cancel out the parasitic capacitance effect of the third via. This intermediary via is positioned adjacent to the parasitic via and connected to the reference plane, creating an opposing capacitive effect that neutralizes the distortion without requiring complex manufacturing changes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical parameters of the via structure by adding an additional via with specific positioning and connection characteristics. By adjusting the number, position, and connectivity of vias, the overall parasitic effect is modified to achieve signal distortion cancellation while maintaining standard manufacturing processes

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If reference plane layers are dedicated to minimize parasitic inductance, then inductive interference is reduced, but parasitic capacitance increases due to unused via portions and mounting pads

Engineering Contradiction:
Improveparasitic inductanceVSAvoidparasitic capacitance
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful parasitic capacitance effect of unused via portions into a beneficial counteracting force. By strategically positioning additional vias near the parasitic vias, their previously harmful capacitive effects are harnessed to cancel out signal distortion, transforming a disadvantage into an advantage

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

Instead of trying to eliminate or isolate parasitic vias, the patent inverts the approach by adding more vias that create opposing parasitic effects. Rather than removing the problem, it introduces elements that generate counterbalancing interference, effectively canceling the distortion through inverted reasoning

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces or eliminates signal distortion caused by parasitic effects, maintaining signal strength and integrity while avoiding the cost and topology constraints of traditional solutions, thus enhancing the performance of printed circuit boards.

Implementation Method 1

Parasitic capacitance is the capacitive interference that results from the storage of stray charges in the PCB elements that make up the conductive pathway between electronic components

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

Parasitic inductance is the inductive interference that results from the storage of a stray magnetic field around the PCB elements that make up the conductive pathway between electronic components

Methodology Applied
Scientific EffectParasitic inductance: Inductor

Implementation Method 3

As the current oscillates its polarity at high frequencies in these conductors, a magnetic field establishes and collapses around the conductors at a corresponding frequency that operates to resist changes in the current

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS7667980B2Printed circuit boards for countering signal distortion
Publication Date: 2010.02.23 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US7667980B2 patent drawing
  • US7667980B2 patent drawing
  • US7667980B2 patent drawing

AI summary

Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.