PCB Plane Stackup for FPGA Jitter Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Printed circuit boards (PCBs) contribute to jitter in semiconductor devices like FPGAs due to local voltage supply noise, caused by parasitic inductive, capacitive, and resistive loads, which result in voltage fluctuations and increased power supply noise.
Innovation Solution
The stackup of PCB planes is controlled to minimize inductance between the FPGA and PCB voltage planes, with core supply planes placed closer to the FPGA and I/O supply planes farther away, optimizing the placement of power, signal, and ground planes to reduce ripple and transient noise on voltage rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power supply planes are placed in the middle of the board without specific ordering, then manufacturing is simplified, but noise coupling between adjacent planes increases and jitter performance deteriorates
Solution Approach 1:
The patent segments power supply planes into distinct groups (core power planes and I/O power planes) and assigns them specific locations in the stackup. Core power planes are placed closer to the device while I/O power planes are placed farther away, creating clear separation between different power domains to prevent noise coupling.
Solution Approach 2:
The patent applies different placement strategies to different types of power planes based on their functional requirements. Core power planes requiring low noise are positioned adjacent to the device with dedicated ground planes, while I/O power planes handling higher noise are positioned farther away, optimizing each plane's location for its specific function.
2Power
If I/O power supply planes are placed closer to the device than core supply planes, then I/O circuitry power delivery is improved, but noise from I/O planes couples onto core power planes and increases jitter
Solution Approach 1:
The patent extracts I/O power planes from proximity to the core device area and places them in outer layers farther from the device. This separation removes the noise source (I/O power planes) from the sensitive area where core power planes are located, preventing noise coupling while maintaining power delivery capability through proper via placement.
Solution Approach 2:
The patent introduces ground planes as intermediary layers between I/O power planes and core power planes. These ground planes act as noise barriers and reference planes that prevent direct coupling of noise from I/O power planes to core power planes, mediating the electromagnetic interaction between the two power domains.
3Reliability
If multiple ground planes are placed between signal layers, then signal integrity is improved, but PCB complexity and manufacturing difficulty increase
Solution Approach 1:
The patent establishes a predetermined stackup structure where ground planes are systematically placed between signal layers according to specific rules. This preliminary design approach defines the exact sequence and positioning of ground planes during the PCB design phase, ensuring signal integrity requirements are met while maintaining manufacturing feasibility through standardized patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces jitter by minimizing inductance and transient noise, enhancing the RMS voltage level and reducing variability in delay, thereby improving jitter performance in timing-critical circuits.
Implementation Method 1
The stackup of PCB planes is controlled to minimize inductance between the FPGA and PCB voltage planes
Implementation Method 2
Parasitic inductive, capacitive, and resistive loads along the lines supplying power and signals to elements in the FPGA
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A model and method are provided for lowering device jitter by controlling the stackup of PCB planes (1 -24) so as to minimize inductance between a FPGA (105) and PCB voltage planes (1 -24) for critical core voltages within the FPGA (105). Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.