PCB Plating Bump Height Control via Segmented Base and Top Layers

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Solution Overview

Problem

Existing methods for manufacturing printed wiring boards with plating bumps face challenges in achieving consistent bump heights and reducing void occurrence, particularly due to differences in aspect ratios and plating layer thicknesses in the formation of first and second bumps.

Innovation Solution

A method involving the formation of a base insulating layer, conductor layer, and solder resist layer with specific openings for first and second conductor pads, followed by forming base and top plating layers with controlled thicknesses and recesses, and reflowing the top plating layers to achieve bumps with consistent heights and reduced voids.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the second opening has a smaller diameter than the first opening, then the second bump has a smaller diameter, but the aspect ratio of the second opening increases making plating more difficult and increasing void occurrence

Engineering Contradiction:
Improvebump diameter controlVSAvoidvoid occurrence
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming a base plating layer in the second opening before forming the top plating layer. This base plating layer serves as a preliminary structure that fills the deep, narrow opening and provides a foundation for the top plating layer, preventing void formation during subsequent plating processes. The base plating layer is formed to a thickness that ensures complete coverage of the opening depth, addressing the void occurrence issue before the top plating layer is applied.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the plating process into two distinct stages: forming a base plating layer first, then forming a top plating layer on top of it. This segmentation allows each plating layer to be optimized independently - the base plating layer addresses the deep opening geometry while the top plating layer provides the final bump structure. This two-stage approach prevents voids by ensuring proper material deposition in the difficult-to-reach narrow opening before completing the bump formation.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If the second top plating layer has a greater thickness than the first top plating layer, then the second bump can reach consistent height after reflow, but the plating process becomes more complex

Engineering Contradiction:
Improvebump height consistencyVSAvoidplating process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by making the second top plating layer thicker than the first top plating layer. This local variation in thickness compensates for the greater depth of the second opening, ensuring that after reflow, both bumps reach substantially the same height. The different thicknesses are precisely controlled during plating to account for the different opening geometries, achieving uniform bump heights despite the asymmetric structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the plating parameters specifically for the second opening, including increasing the thickness of both the base plating layer and the top plating layer compared to the first opening. These parameter adjustments are made to compensate for the smaller diameter and greater depth of the second opening, ensuring that the final bump dimensions and heights are consistent across both openings after the reflow process.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If different thicknesses of top plating layers are formed in the first and second openings, then consistent bump heights are achieved after reflow, but the plating process requires precise control

Engineering Contradiction:
Improvebump height uniformityVSAvoidplating thickness control
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent uses preliminary action by first forming a base plating layer of controlled thickness in each opening before forming the top plating layer. This base layer establishes a known starting thickness that compensates for the different opening depths. Then, the top plating layer is formed with a controlled thickness differential - thicker in the second opening than in the first - to ensure that after reflow, both bumps reach the same height. This two-stage thickness control simplifies the overall precision requirement compared to attempting to form the entire bump in a single plating step.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method ensures stable bump formation with consistent heights and reduced void occurrence, enhancing connection reliability between bumps and electronic components.

Implementation Method 1

reflowing the first top plating layer, and the forming of the second bump includes forming a second base plating layer in the second opening, forming a second top plating layer on the second base plating layer such that the second top plating layer has an upper surface that is higher than the uppermost position of an upper surface of the first top plating layer, and reflowing the second top plating layer

Methodology Applied
Scientific EffectReflow: Melting

Data Source

PatentUS11109481B2Method for manufacturing printed wiring board and printed wiring board
Publication Date: 2021.08.31 IBIDEN CO LTD
  • US11109481B2 patent drawing
  • US11109481B2 patent drawing
  • US11109481B2 patent drawing

AI summary

A method for manufacturing a printed wiring board includes forming a base insulating layer, forming a conductor layer on the base layer, forming a solder resist layer on the base layer such that the resist layer covers the conductor layer, forming first opening exposing a first pad of the conductor layer, forming second opening exposing a second pad of the conductor layer and having diameter smaller than diameter of the first opening, forming a first bump on the first pad, and forming a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump includes a first base plating layer and a first top plating layer, and the second bump includes a second base plating layer and a second top plating layer having upper surface higher than the uppermost position of upper surface of the first top layer.