Printed Wiring Board Secondary Plating Reduction
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Solution Overview
Problem
High-density printed wiring boards require a lengthy secondary plating step, leading to increased manufacturing costs and variations in wiring dimensions.
Innovation Solution
A printed wiring board with a conductive pattern comprising a first conductive portion formed using a semi-additive method and a second conductive portion formed through secondary plating, where the average width of the wiring portions is 10 μm to 50 μm and the average thickness of the second conductive portion is 1 μm to 8.5 μm, reducing the volume and time required for secondary plating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If secondary plating is performed to secure the cross-sectional area of minimal wiring in high-density printed wiring boards, then the wiring cross-sectional area is sufficient, but the manufacturing time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by forming a conductive foundation layer with controlled thickness (1μm to 8.5μm) before the secondary plating step. This foundation layer is prepared in advance with precise thickness control through the semi-additive method, so that when secondary plating is performed, the required cross-sectional area is achieved with minimal additional plating time. The foundation layer serves as a pre-prepared base that reduces the burden on the subsequent secondary plating process.
Solution Approach 2:
The patent applies parameter changes by precisely controlling the thickness of the conductive foundation layer within the range of 1μm to 8.5μm. This parameter control allows the secondary plating to achieve the necessary cross-sectional area with minimal thickness addition, thereby reducing plating time. By optimizing the foundation layer thickness parameter, the patent balances the need for sufficient wiring cross-section with the need to minimize secondary plating duration.
2Strength
If secondary plating is performed for extended periods to ensure adequate wiring cross-sectional area, then the wiring strength is sufficient, but variations in wiring dimensions increase
Solution Approach 1:
The conductive foundation layer is formed in advance with controlled thickness (1μm to 8.5μm) using the semi-additive method, providing a stable base before secondary plating. This preliminary preparation ensures that the foundation layer has sufficient thickness to support the wiring structure, reducing the need for extended secondary plating that would otherwise be required to achieve adequate wiring strength. The pre-formed foundation layer minimizes dimensional variations by providing a consistent starting point.
Solution Approach 2:
The patent controls the foundation layer thickness within the specific range of 1μm to 8.5μm to optimize the balance between wiring strength and dimensional consistency. This parameter control ensures that the foundation layer is thick enough to provide structural support and minimize variations, while not so thick that it requires excessive secondary plating time that would introduce dimensional variations. The controlled thickness parameter directly impacts both wiring strength and dimension consistency.
3Productivity
If the conductive foundation layer thickness is increased to reduce secondary plating time, then manufacturing efficiency improves, but the complexity of controlling plating uniformity increases
Solution Approach 1:
The patent specifies the foundation layer thickness within the range of 1μm to 8.5μm to optimize the balance between productivity and process control complexity. This parameter range is thick enough to reduce secondary plating time and improve manufacturing efficiency, while remaining thin enough to maintain plating uniformity and avoid excessive complexity in process control. The controlled thickness parameter enables efficient secondary plating without compromising plating quality.
Solution Approach 2:
The patent applies partial action by forming a foundation layer with thickness (1μm to 8.5μm) that is sufficient to reduce secondary plating time but not excessively thick. This partial thickness provides enough support to minimize secondary plating requirements while avoiding the complexities associated with forming very thick foundation layers. The foundation layer thickness is optimized to provide just enough reduction in secondary plating time without introducing excessive process control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and minimizes variations in wiring dimensions by shortening the secondary plating step while maintaining high wiring density and preventing peeling of the first conductive portion.
Implementation Method 1
exposure to and development of the photoresist film
Implementation Method 2
forming a first conductive portion by plating an opening of the resist pattern on the conductive foundation layer
Implementation Method 3
coating a second conductive portion on an outer surface of the first conductive portion by plating
Data Source
AI summary
A printed wiring board according to an aspect of the present invention includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated, the conductive pattern running on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μn or greater to smaller than 8.5 μm.