PCB Planarization via Mechanical Polishing and Chemical Etching

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Solution Overview

Problem

Conventional Chemical Mechanical Polishing (CMP) processes are expensive and unsuitable for large-area applications, limiting their effectiveness in fine circuit formation on printed circuit boards (PCBs).

Innovation Solution

A method involving mechanical polishing and chemical etching is used to remove excess metal layers from PCBs, replacing the expensive CMP process, allowing for the formation of fine circuit patterns on large areas at reduced costs and in less time, utilizing a dielectric layer with a negative pattern and conductive metals like gold, silver, and copper.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If CMP process is used for planarization, then surface quality and thickness uniformity are improved, but manufacturing cost increases significantly

Engineering Contradiction:
Improvesurface qualityVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent divides the planarization process into two separate stages: mechanical polishing to remove protrusions and achieve initial flatness, followed by chemical etching to achieve final surface quality. This segmentation allows each process to be optimized independently and reduces the need for expensive CMP equipment while maintaining manufacturing precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent replaces the mechanical-chemical combined CMP system with a sequential mechanical polishing followed by chemical etching system. This substitution eliminates the need for complex CMP apparatus while achieving comparable or superior surface quality through the combined effect of mechanical removal and chemical smoothing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If CMP process is used for planarization, then thickness uniformity is improved, but process time increases

Engineering Contradiction:
Improvethickness uniformityVSAvoidprocess time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the planarization into distinct mechanical polishing and chemical etching steps, allowing parallel processing and optimization of each stage. The mechanical polishing quickly removes material to achieve gross flatness, while chemical etching simultaneously smooths the surface, reducing total process time compared to sequential CMP operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters by using mechanical polishing with controlled pressure and speed to rapidly remove protrusions, followed by chemical etching with optimized concentration and temperature. This parameter optimization enables faster material removal while maintaining thickness uniformity, reducing overall process time.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If CMP process is used for planarization, then surface quality is improved, but applicability to large areas is reduced

Engineering Contradiction:
Improvesurface qualityVSAvoidprocessable area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent divides the large-area substrate processing into mechanical polishing and chemical etching steps that can be independently scaled. Mechanical polishing can be performed on large areas using simple polishing pads or belts, and chemical etching can be applied uniformly across large surfaces through immersion or spraying, enabling both high surface quality and large-area applicability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent replaces the complex mechanical CMP system with a combination of simpler mechanical polishing and chemical etching processes. The chemical etching step, in particular, can be easily scaled to large areas through immersion tanks or spray systems, eliminating the area limitations of mechanical CMP while maintaining surface quality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the economical and efficient formation of fine circuit patterns on large areas, reducing process time and costs, while ensuring high reliability and compatibility with imprinting processes.

Implementation Method 1

a mechanical removal process... in which a mechanical removal function is realized by the polishing particles in the slurry 13 and the surface protrusions 14 of the pad 12

Methodology Applied
Scientific EffectMechanical abrasion: Abrasion

Implementation Method 2

a chemical removal process... in which a chemical removal function is realized by the chemical component in the slurry 13

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS7562447B2Method of manufacturing printed circuit board for fine circuit formation
Publication Date: 2009.07.21 SAMSUNG ELECTRO MECHANICS CO LTD
  • US7562447B2 patent drawing
  • US7562447B2 patent drawing
  • US7562447B2 patent drawing

AI summary

Disclosed is a method of manufacturing a printed circuit board for fine circuit formation, in which an unnecessary metal layer formed on the upper portion of a circuit pattern is removed through mechanical polishing and then chemical etching. In place of expensive chemical mechanical polishing, in the method of the invention, mechanical polishing and chemical etching are continuously applied to thus sequentially remove and planarize the unnecessary metal layer. Thereby, through an inexpensive, simple, and continuous process, the planarization procedure can be precisely performed, thus making it possible to apply the method to large areas and economically realize a fine circuit pattern.