Power Ground Ball Pad Array for PCB IR Drop Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In microelectronic systems, board-level IR drop is significant due to increased current requirements and reduced supply voltage noise margins, affecting the operation of high-speed devices, particularly in complex printed circuit boards with long power distribution paths and non-ideal routing.
Innovation Solution
A high-density multi-layer printed circuit board with a laminated core and build-up layers featuring a power/ground ball pad array, where power and ground ball pads are arranged in interdigitated comb or ladder patterns with microvias connecting them to internal conductive layers, reducing IR drop by minimizing voltage loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power distribution paths are used in complex PCBs, then the PCB can accommodate various components and routing, but board-level IR drop increases significantly due to long distribution paths and non-ideal routing
Solution Approach 1:
The power distribution system is segmented into multiple parallel paths using separate power planes and via structures. The patent divides the power delivery network into distinct segments with dedicated power planes for different voltage domains, allowing current to be distributed through multiple shorter paths rather than a single long path, thereby reducing overall IR drop while maintaining the ability to accommodate various components.
Solution Approach 2:
The patent transitions from planar, two-dimensional power routing to three-dimensional power distribution by utilizing multiple stacked planes and vertical via connections. This vertical dimension allows current to flow through shorter, more direct paths between power sources and loads, reducing the effective distribution path length and minimizing IR drop while maintaining system functionality.
2Adaptability or versatility
If the number of pins and I/O pads are increased to support higher functionality, then device capability is enhanced, but package and board IR drop become more significant due to increased current requirements
Solution Approach 1:
The power distribution system is divided into multiple dedicated power planes, each serving specific voltage domains or functional blocks. This segmentation allows high-current I/O pads to be served by dedicated power paths with lower impedance, reducing IR drop at high-functionality pins while maintaining the ability to support increased device capability.
Solution Approach 2:
The patent implements local power distribution by providing dedicated power planes and via structures adjacent to high-current I/O pads and functional blocks. This local quality approach ensures that high-current paths have optimized, low-impedance power delivery right at the point of consumption, reducing IR drop without limiting the number of pins or I/O capabilities.
3Quantity of substance
If power distribution traverses multiple layers in BGA packages, then connection density is increased, but path resistance increases due to irregular shapes and limited layers available
Solution Approach 1:
The patent utilizes vertical stacking of multiple power planes and via connections to create three-dimensional power distribution paths. This vertical dimension provides additional routing options and shorter paths for power delivery, increasing connection density while reducing the resistance associated with traversing multiple layers by optimizing the vertical power delivery architecture.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A printed circuit board (20) includes a laminated core (210) including at least an internal conductive layer (L2, L5), and a build-up layer (212, 214) on the laminated core (210). The build-up layer (212, 214) includes a top conductive layer (L1, L6). Microvias (220a, 220b) are disposed in the build-up layer (212, 214) to electrically connect the top conductive layer (L1, L6) with the internal conductive layer (L2, L5). A power/ground ball pad array is disposed in the top conductive layer (L1). The power/ground ball pad array includes power ball pads (302) and ground ball pads (402) arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area (2a, 2b) that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads.