PCB Power Plane Impedance Reduction via Segmented Ground Planes
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Solution Overview
Problem
Prior art printed circuit boards (PCBs) suffer from high impedance due to the thick dielectric layer separating the power plane and ground plane, limiting bandwidth and performance, especially in high-frequency applications.
Innovation Solution
The method involves forming additional ground planes in the routing layer of the power plane to decrease the distance between the power and ground planes, increasing mutual inductance and reducing loop inductance, thereby decreasing impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thick dielectric layer is used to separate the power plane and ground plane for manufacturing and cost considerations, then production cost is reduced and manufacturing is simplified, but the impedance of the power source increases and bandwidth is limited
Solution Approach 1:
The invention divides the ground plane into multiple segments: a first ground plane on one side of the power plane and a second ground plane on the other side. This segmentation allows the system to achieve low impedance characteristics without requiring a uniformly thick dielectric layer, thus resolving the contradiction between manufacturing simplicity and power source impedance.
Solution Approach 2:
The invention applies different dielectric layer thicknesses in different locations: a first dielectric layer with a first thickness and a second dielectric layer with a second thickness. This local quality variation allows optimization of impedance characteristics in specific areas while maintaining overall manufacturing feasibility.
2Ease of manufacture
If the distance between the power plane and ground plane is increased for manufacturing reasons, then production is simplified, but loop inductance increases and power impedance increases
Solution Approach 1:
By segmenting the ground plane into first and second ground planes located on opposite sides of the power plane, the invention creates multiple return paths for current. This reduces the effective loop area and loop inductance without requiring the power plane and ground plane to be in close proximity throughout, thus maintaining manufacturing simplicity while reducing power impedance.
Solution Approach 2:
The invention transitions from a single-plane ground configuration to a three-dimensional arrangement with ground planes on both sides of the power plane. This dimensional change creates multiple coupling paths and reduces the effective distance for magnetic flux, thereby reducing loop inductance and power impedance while maintaining manufacturable dielectric layer thicknesses.
3Reliability
If additional ground planes are deposited in the routing layer of the power plane, then coupling between power source and ground increases and impedance decreases, but device complexity increases
Solution Approach 1:
The invention segments the ground plane into first and second ground planes that can be deposited in the same routing layer as the power plane. This segmentation approach increases coupling and reduces impedance while maintaining a regular layered structure that does not significantly increase manufacturing complexity.
Solution Approach 2:
The invention combines the first and second ground planes with the power plane in the same routing layer, creating a tightly coupled structure. This merging of elements in the same layer maximizes coupling efficiency and reduces impedance without requiring additional routing layers or complex three-dimensional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases input impedance, increases bandwidth, and enhances stability by increasing coupling between the power source and ground, leading to improved performance in high-frequency applications.
Implementation Method 1
a dielectric layer is disposed between the first layer and the second layer of the printed circuit board for insulating the first layer from the second layer
Implementation Method 2
depositing other ground planes in a routing layer of a power plane... increasing mutual inductance and reducing loop inductance
Implementation Method 3
the closer the power plane and the ground plane, the smaller the loop inductance between the power plane and the ground plane, and as those skilled in the art recognize, the smaller the loop inductance, the lower the power impedance within a frequency range
Data Source
AI summary
A method for decreasing impedance of a power source in a printed circuit board includes: (a) forming a first metal plane over a first layer of the printed circuit board; (b) forming a second metal plane and a third metal plane over a second layer of the printed circuit board; (c) forming a dielectric layer between the first layer and the second layer of the printed circuit board for insulating the first layer from the second layer; and (d) connecting the second metal plane to an electric potential different from an electric potential of the first metal plane and the third metal plane.