Multi-Layer PCB Power Routing for Parasitic Reduction
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Solution Overview
Problem
In printed wiring boards, large currents flowing into the switch output stage are affected by parasitic components such as parasitic inductance and resistance, leading to high-level drops or ringing of the switching voltage.
Innovation Solution
A multi-layer printed wiring board design with thick and short power and ground lines, interlayer connections, and an insulating layer thinner than 200 μm, where the second wiring pattern has greater width, thickness, or conductivity than the first, and is positioned to bypass terminal rows, reducing parasitic components and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional printed wiring board design is used, then manufacturing is simpler, but parasitic components (inductance and resistance) increase causing voltage drops and ringing
Solution Approach 1:
The patent transitions from conventional two-dimensional surface wiring to three-dimensional multi-layer wiring structure. Power lines and ground lines are arranged on different layers and connected through vertical via holes, creating a three-dimensional conductive path that reduces parasitic inductance and resistance while maintaining compact form factor.
Solution Approach 2:
The patent embeds power lines and ground lines within the multi-layer substrate structure, nesting conductive paths inside the board rather than only on the surface. The via holes nest vertically through layers, and the thick wire patterns are integrated within the substrate thickness, creating a compact nested wiring architecture.
2Reliability
If thick and short power and ground lines are used, then parasitic components are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes key parameters of the wiring structure: increasing wire thickness (e.g., 10-50 μm), reducing wire length through optimized routing, decreasing insulating layer thickness (50-200 μm), and adjusting via hole dimensions. These parameter optimizations collectively reduce parasitic components while establishing new manufacturing specification standards.
Solution Approach 2:
The patent applies different wire thicknesses and insulating layer thicknesses at different locations and layers. Power lines and ground lines have optimized local dimensions tailored to their specific functional requirements, with thicker wires where high current flows and thinner insulating layers where parasitic reduction is most critical.
3Reliability
If interlayer connections are added to bypass terminal rows, then electrical performance improves, but device complexity increases
Solution Approach 1:
The patent segments the power and ground connections into multiple independent paths across different layers. Instead of a single long surface trace, the current is divided into multiple shorter segments connected by vertical vias, reducing the total parasitic inductance and resistance of the power delivery network.
Solution Approach 2:
The via holes serve as intermediary elements that connect power lines and ground lines between different layers. These vertical conductors act as mediators that enable three-dimensional current flow paths, bypassing the limitations of two-dimensional surface wiring and reducing parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively inhibits parasitic components, reducing high-level drops and ringing of the switching voltage, ensuring a more reliable switching operation even under large current conditions.
Implementation Method 1
an interlayer connection electrically conducting the first wiring pattern and the second wiring pattern to bypass at least a portion of the power terminal row or the ground terminal row
Implementation Method 2
a second wiring pattern of the power line and a second wiring pattern of the ground line are overlapped with each other so that respective currents flow in opposite directions
Data Source
AI summary
A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.