PCB Protruding Patterns for Circuit Adhesion
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Solution Overview
Problem
In high-data and high-speed processing applications, such as package flip chip ball grid array (FCBGA) substrates, securing adhesion of circuits is a significant challenge due to the increasing demand for materials with low dielectric loss and thermal expansion, and existing methods like semi-additive processes have limitations in ensuring strong adhesion and preventing pattern delamination.
Innovation Solution
The solution involves forming pattern holes in the insulating layer where line patterns are to be formed, which are then filled with conductors during plating to create protruding patterns that structurally support the line patterns, enhancing adhesion by optimizing curing and desmear conditions of the insulating material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If materials with low dielectric loss and low CTE are used, then signal integrity and thermal stability are improved, but adhesion of the circuit is worsened
Solution Approach 1:
The patent applies preliminary action by forming protruding patterns in the insulating layer before depositing the line patterns. These protrusions create mechanical interlocking features that enhance adhesion before the actual circuit formation, allowing the use of low-Df and low-CTE materials without sacrificing adhesion.
Solution Approach 2:
The patent applies local quality by creating protruding patterns only in specific locations where adhesion is needed, rather than modifying the entire insulating layer. This allows the bulk material to maintain its low dielectric loss and low CTE properties while providing localized adhesion enhancement at the interface with the line patterns.
2Ease of manufacture
If conventional plating processes are used, then manufacturing simplicity is maintained, but pattern delamination occurs
Solution Approach 1:
The patent performs preliminary action by forming protruding patterns through etching or molding before the plating process. This preliminary structuring of the insulating layer creates mechanical interlocking features that prevent delamination during subsequent conventional plating operations, maintaining manufacturing simplicity while improving reliability.
3Reliability
If the insulating layer is made thinner to reduce signal loss, then signal integrity is improved, but adhesion becomes more difficult to secure
Solution Approach 1:
The patent applies local quality by concentrating adhesion enhancement features (protruding patterns) at the critical interface between the insulating layer and line patterns, rather than increasing the overall thickness of the insulating layer. This allows thin insulating layers to maintain both signal integrity and adhesion.
Solution Approach 2:
The patent transitions from a two-dimensional planar interface to a three-dimensional interlocking interface by creating protruding patterns. This dimensional change increases the effective bonding area and mechanical interlocking without increasing the vertical thickness of the insulating layer, thus maintaining signal integrity while improving adhesion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves adhesion strength, prevents pattern delamination, and allows for better insulation and integration of line patterns, addressing the limitations of existing methods in securing circuit adhesion.
Implementation Method 1
When forming the line pattern by plating, or the like, the plurality of pattern holes are also filled with a conductor
Data Source
AI summary
A printed circuit board includes an insulating layer having a first surface and a second surface opposing the first surface; and a first wiring including a first line pattern disposed on the first surface of the insulating layer, and a plurality of first protruding patterns penetrating a portion of the insulating layer from the first surface and connected to the first line pattern, respectively, such that the plurality of first protruding patterns overlap the first line pattern in a plan view of the printed circuit board.