Printed Wiring Board Recesses for Ion Migration Prevention
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Solution Overview
Problem
Existing printed wiring boards face challenges with ion migration between conductor patterns, leading to potential short circuiting due to narrow pattern widths and intervals, especially as IC chips miniaturize and integrate further.
Innovation Solution
A printed wiring board design featuring conductor patterns with widths and intervals of 3 μm or less, along with recesses etched into the insulating layer between these patterns, reducing the electric field strength and preventing metal deposition, thereby minimizing ion migration and short circuiting risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductor patterns are spaced closely to increase integration density, then productivity and miniaturization are improved, but ion migration and short circuiting occur due to high electric field strength
Solution Approach 1:
The invention transitions from a two-dimensional planar surface to a three-dimensional structured surface by forming recess portions between conductor patterns. This dimensional change allows the electric field to be confined and offset within the recess regions, enabling close spacing of conductor patterns (3 μm or less) while preventing ion migration and short circuiting through the insulating layer.
Solution Approach 2:
The invention applies different structural properties to different regions: the recess portions between conductor patterns have a depth of 0.1-2.0 μm to offset and contain electric fields, while the conductor patterns themselves maintain standard dimensions. This localized structural modification addresses the high electric field problem only where needed, between adjacent conductors, without affecting overall circuit functionality.
2Length of moving object
If conductor pattern width and interval are reduced to 3 μm or less, then miniaturization is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The recess portions are formed in the insulating layer before the conductor patterns are deposited. This preliminary action creates pre-defined spacing regions that guide and constrain the conductor pattern formation process, making it easier to achieve precise 3 μm or less dimensions and intervals without requiring extremely high manufacturing precision in subsequent steps.
3Reliability
If recess portions are formed to offset electric fields, then ion migration is reduced, but device complexity increases
Solution Approach 1:
The recess portions create a controlled porous or cavity structure within the insulating layer. These recesses act as electric field offset regions that prevent ion migration between adjacent conductor patterns. The structured insulating layer with recess portions maintains its insulating function while adding the necessary complexity only where required for reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The recesses in the insulating layer between conductor patterns reduce ion migration and short circuiting by offsetting the electric field and filling voids, enhancing the reliability and stability of the printed wiring board.
Implementation Method 1
the recess portions have a depth in a range of 0.1 μm to 2.0 μm relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other
Data Source
AI summary
A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 μm or less and that the conductor patterns have a pattern interval of 3 μm or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 μm to 2.0 μm relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.