Multi-layer PCB Shielding Element for EMI Reduction

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Solution Overview

Problem

Miniaturization of printed circuit boards leads to reduced layout area, causing electromagnetic interference (EMI) to nearby electronic devices due to the lack of shielding for signal layers.

Innovation Solution

A multi-layer printed circuit board (MLPCB) structure with a shielding element on the first layout layer and signal wires on the second layout layer, where a predefined proportion of the wires is covered by the shielding element's projection plane, effectively reducing EMI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If signal layers are disposed on outer layers of the multilayer printed circuit board, then the layout area is increased, but electromagnetic interference is caused to nearby electronic devices

Engineering Contradiction:
Improvelayout areaVSAvoidelectromagnetic interference
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent moves signal wires from the outer first layout layer to the inner second layout layer, utilizing the third dimension (layer depth) to resolve the contradiction. This dimensional transition allows signals to be transmitted within the board structure rather than on the outer surface, reducing EMI while preserving layout area through multi-layer configuration

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The shielding element acts as an intermediary between the signal wires on the second layout layer and the outer environment. By positioning the shielding element on the first layout layer corresponding to the signal wire locations, it mediates and blocks electromagnetic interference from reaching nearby electronic devices, thus resolving the EMI issue while maintaining the benefits of inner-layer signal routing

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If the size of the printed circuit board is reduced, then miniaturization is achieved, but the layout area is reduced

Engineering Contradiction:
Improvelayout areaVSAvoidPCB size
Core Design Contradiction:
Area of stationary objectVSLength of moving object

Solution Approach 1:

The patent utilizes the vertical dimension by implementing a multi-layer structure with at least two layout layers. This allows signal wires to be routed on the inner second layout layer while pads connect to external connectors on the outer first layout layer, effectively increasing the usable layout area within the same PCB footprint and enabling miniaturization without sacrificing layout capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces electromagnetic interference to nearby electronic devices by shielding the signal wires, improving the layout efficiency without increasing the PCB size.

Implementation Method 1

The first layout layer includes a shielding element and at least one pad. The shielding element is configured to provide the grounding voltage. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS20150305143A1Multi-layer printed circuit board structure, connector module and memory storage device
Publication Date: 2015.10.22 PHISON ELECTRONICS
  • US20150305143A1 patent drawing
  • US20150305143A1 patent drawing
  • US20150305143A1 patent drawing

AI summary

A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.