PCB Signal Timing Control via Delayed Transmission
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Solution Overview
Problem
Current printed circuit board (PCB) manufacturing methods face challenges in synchronizing signal timing between elements due to uneven distances between components, leading to increased design complexity, inefficiency, and wasted space.
Innovation Solution
A PCB design that includes a sending element, receiving elements, and a control unit with a comparison table storing information about the wires, allowing the control unit to generate and delay control signals to synchronize signal timing across receiving elements, regardless of wire lengths or transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire lengths are equalized to synchronize signal timing, then signal timing is synchronized, but layout complexity increases and PCB space is wasted
Solution Approach 1:
The patent extracts the signal timing synchronization function from the physical wire length design. Instead of making wires equal length to achieve timing synchronization, the invention separates the timing control function into a dedicated control unit that actively manages signal delivery time, allowing wires to have different lengths while maintaining synchronized arrival times at receiving elements.
Solution Approach 2:
The invention changes the parameter being controlled from wire length (physical dimension) to transmission time (temporal parameter). The control unit stores transmission time information for different wires and adjusts signal delivery timing dynamically, transforming the problem from a spatial constraint to a temporal control problem.
2Reliability
If wire lengths are equalized to synchronize signal timing, then signal timing is synchronized, but layout efficiency decreases
Solution Approach 1:
The patent removes the constraint that wire length must be equalized for timing synchronization. By extracting the timing control function to a separate control unit, the layout process is freed from the requirement of calculating and adjusting wire lengths, allowing layout engineers to place components and routes more efficiently without timing synchronization overhead.
3Reliability
If wire lengths are equalized to synchronize signal timing, then signal timing is synchronized, but PCB space utilization is reduced
Solution Approach 1:
The invention transforms the timing synchronization approach from spatial adjustment (equalizing wire lengths) to temporal control (adjusting signal delivery times). This allows the PCB layout to use minimal wire lengths necessary for connectivity, maximizing space utilization while the control unit compensates for timing differences through active time management.
Data Source
AI summary
A printed circuit board includes a sending element, a plurality of receiving elements, and a control unit. The sending element is configured to generate a sending signal. The receiving elements are configured to receive a control signal respectively. The control unit is coupled to the sending element through a first wire and to the receiving elements through a plurality of second wires. The control unit is provided with a comparison table that stores related information of the second wires. When receiving the sending signal, the control unit generates the control signals according the related information of the second wires. At least one of the control signals is transmitted to the corresponding receiving element, and the rest of the control signals are delayed for a preset time and then transmitted to the rest of the receiving elements.