Printed Wiring Board Solder Bump Geometry for Thermal Stress
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Solution Overview
Problem
The challenge in printed wiring boards is the potential destruction of solder bumps due to thermal expansion differences between IC chips and core substrates, leading to reliability issues during temperature changes.
Innovation Solution
A printed wiring board design with conductor pads arranged at a pitch of 200 μm or less, featuring solder bumps with a height-to-diameter ratio of 0.55 to 1.0, and a flattened solder resist layer with controlled surface roughness to enhance stress absorption and prevent short-circuits, along with an underfill material to seal gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of conductor pads is reduced to 200 μm or less for high-density mounting, then the productivity and compactness are improved, but the reliability of solder bumps deteriorates due to increased thermal stress concentration
Solution Approach 1:
The patent optimizes the height-to-diameter ratio parameter of solder bumps to a specific range (0.5-1.5) to reduce stress concentration. By changing the geometric parameters of the solder bump structure, the patent achieves both high-density mounting capability and maintained reliability under thermal cycling conditions.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the solder bump height-to-diameter ratio is specifically controlled in the mounting area to provide stress absorption, while the overall board layout maintains high density. This localized optimization of structural parameters resolves the contradiction between density and reliability.
2Reliability
If the height-to-diameter ratio of solder bumps is increased to improve stress absorption, then the reliability is improved, but the manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent defines a specific range for the height-to-diameter ratio (0.5-1.5) that balances stress absorption capability with manufacturability. This parameter optimization ensures that solder bumps are tall enough to absorb thermal stress but not so tall that they become difficult to manufacture with consistent precision.
Solution Approach 2:
The patent applies a moderate height-to-diameter ratio that provides sufficient stress absorption without excessive height that would complicate manufacturing. This partial action approach achieves the necessary reliability improvement without over-engineering the solder bump dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves connection and insulation reliability by absorbing stress and preventing voids in the underfill resin, while reducing the risk of solder bump failure and short-circuits, thus enhancing heat cycle resistance.
Implementation Method 1
the ratio (H/D) of a height H of the solder bump from the surface of the solder resist layer to an opening diameter D of the opening is about 0.55 to about 1.0
Implementation Method 2
an under fill material or resin for sealing a gap or space defined between electronic parts mounted through the solder bumps and the solder resist layer
Data Source
AI summary
A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.