PCB Solder Mask Void Regions for Insertion Loss Reduction
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Solution Overview
Problem
High-speed electronic applications face increased insertion loss due to the high dissipation factor of solder mask on printed circuit boards, which negatively impacts signal integrity and requires additional components like cables and re-timers, making the solution costly and impractical for long-term viability.
Innovation Solution
Introducing void regions in the solder mask layer to decrease the overall use of solder mask while maintaining protection against solder shots and electrical shorts, thereby reducing insertion loss and enhancing signal strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder mask is applied to protect traces and prevent solder shots, then protection and prevention are improved, but insertion loss increases due to high dissipation factor
Solution Approach 1:
The patent applies local quality by creating void regions at specific locations along the trace path where solder mask is removed to reduce insertion loss, while maintaining solder mask coverage in other areas to provide protection. This selective application allows different regions of the PCB to have different properties - protected regions for reliability and void regions for signal integrity.
Solution Approach 2:
The solder mask layer is segmented into covered regions and void regions. Instead of applying continuous solder mask coverage, the patent divides the trace path into segments where solder mask is applied and segments where it is removed, allowing optimization of both protection and signal transmission characteristics in different areas.
2Reliability
If solder mask is applied to protect traces, then reliability is improved, but signal integrity deteriorates due to increased insertion loss
Solution Approach 1:
The patent implements local quality by creating zones with different solder mask coverage along the trace path. Void regions are positioned at critical locations where signal integrity is most affected by insertion loss, while maintaining protection in other areas. This allows optimization of signal transmission in specific locations without compromising overall trace protection.
3Manufacturing precision
If additional components like cables and re-timers are added to compensate for insertion loss, then signal integrity is maintained, but device complexity and cost increase
Solution Approach 1:
The patent extracts the problematic solder mask material from specific regions along the trace path to reduce insertion loss. By removing the solder mask in void regions, the design eliminates the source of signal degradation rather than adding compensatory components, thereby maintaining signal integrity while reducing device complexity.
4Manufacturing precision
If solder mask coverage is reduced to decrease insertion loss, then signal integrity is improved, but protection against solder shots and electrical shorts deteriorates
Solution Approach 1:
The patent applies local quality by creating void regions at specific locations where signal integrity is most affected by insertion loss, while maintaining solder mask coverage in other areas to provide protection against solder shots and electrical shorts. This selective approach allows optimization of both signal transmission and protective functions in different regions.
Solution Approach 2:
The solder mask coverage is segmented into protected regions and void regions along the trace path. This segmentation allows the design to maintain protection where needed while reducing insertion loss in critical signal transmission areas, achieving both goals simultaneously through spatial differentiation.
Data Source
AI summary
A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.