PCB Solder Resist Patches for Conductive-Layer Protection
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Solution Overview
Problem
The increasing integration and reduced size of I/O terminals in ICs have made it difficult to form solder resists on PCBs, leading to higher defect rates and increased exposure of conductive layers, which can cause electrical shorts.
Innovation Solution
The PCB design includes a solder resist layer with openings and depressions, and solder resist patches are strategically placed within these features to form an interface, ensuring the conductive layer is not exposed and reducing the risk of electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the degree of integration of ICs is increased and I/O terminal size is reduced, then the integration capability of PCB electrical connection paths is improved, but the difficulty of forming solder resists increases
Solution Approach 1:
The solder resist layer is divided into multiple regions with different thicknesses, creating a multi-layered structure that addresses the manufacturing difficulty while maintaining high integration capability. The segmented thickness distribution allows for better control during the solder resist formation process.
Solution Approach 2:
Different regions of the solder resist layer are given different local properties through varying thickness. The first region has a different thickness than the second region, allowing optimized performance in different areas of the PCB to handle the increased integration and reduced terminal size challenges.
2Reliability
If the difficulty of forming solder resists is increased, then the defect rate of solder resist increases, but the manufacturing process complexity remains the same
Solution Approach 1:
The solder resist layer is formed with predetermined varying thickness regions before the actual soldering process. This preliminary structuring of the solder resist layer with different thickness zones prepares the structure in advance to prevent defects during subsequent manufacturing steps, reducing the defect rate without adding significant complexity.
3Adaptability or versatility
If the spacing between I/O terminals is reduced, then the integration density is improved, but the risk of electrical short increases
Solution Approach 1:
The solution moves from a two-dimensional uniform thickness approach to a three-dimensional varying thickness structure. By introducing thickness variation as an additional dimension, the solder resist provides better insulation and spacing control, reducing electrical short risk while maintaining high integration density with reduced terminal spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the defect rate of solder resists, allowing for higher integration and larger PCBs with more conductive layers, enhancing manufacturing efficiency and reducing electrical shorts.
Implementation Method 1
curing a solder resist layer of an unfinished PCB
Data Source
AI summary
A printed circuit board (PCB) includes a solder resist layer including at least one of an opening and a depression and a solder resist patch disposed in at least one of the opening and the depression to have an interface with the solder resist layer in at least one of the opening and the depression.