PCB Stack-Up Layout With Embedded Capacitor for Low-Inductance Conversion

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Solution Overview

Problem

Existing power converters face issues with parasitic inductance and electromagnetic interference due to conductive traces on printed circuit boards, which degrade performance and efficiency.

Innovation Solution

A multi-layer printed-circuit-board stack with a specific arrangement of conductive and insulating layers, including a parallel-plate capacitor and strategic via holes, minimizes stray inductance and shields control signals from high-power signals, using a five-layer PCB stack-up and floor planning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional PCB wiring is used to connect switches and decoupling capacitor, then the circuit is easy to manufacture, but parasitic inductance increases and performance degrades

Engineering Contradiction:
Improveconverter performanceVSAvoidPCB stack-up complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D PCB routing to 3D multi-layer stack-up architecture. The decoupling capacitor is positioned on an intermediate layer between power and ground planes, creating a three-dimensional configuration that minimizes current loop area and parasitic inductance while maintaining manufacturing feasibility through standard PCB fabrication processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds the decoupling capacitor within the PCB stack-up structure itself, nesting it between the power plane and ground plane layers. This integration eliminates the need for separate external capacitor mounting and reduces the overall current path, thereby minimizing parasitic inductance while keeping the design manufacturable.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Device complexity

If control signals and power signals share the same PCB layers, then the device complexity is reduced, but electromagnetic interference increases

Engineering Contradiction:
ImprovePCB layer arrangementVSAvoidelectromagnetic interference
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the PCB into functionally distinct layers: power planes, ground planes, control signal layers, and decoupling capacitor layers. This segmentation separates high-power switching signals from sensitive control signals, preventing electromagnetic interference while maintaining a manageable multi-layer structure that is still feasible to manufacture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces ground planes and intermediate decoupling capacitor layers as mediators between power signals and control signals. These intermediary layers act as electromagnetic shields, blocking interference from power circuits while allowing control signals to pass through unaffected, thus reducing EMI without requiring complete physical separation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If simple PCB routing is used, then ease of manufacture is improved, but current-handling capability decreases

Engineering Contradiction:
ImprovePCB fabrication simplicityVSAvoidcurrent-handling capability
Core Design Contradiction:
Ease of manufactureVSPower

Solution Approach 1:

The patent designs the PCB stack-up to serve multiple functions simultaneously: the power and ground planes provide both electrical connectivity and electromagnetic shielding; the intermediate layers host both decoupling capacitors and control signals; via holes provide both mechanical alignment and electrical connection. This multi-functionality enables high current-handling capability while maintaining ease of manufacture through standardized PCB processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces stray inductance and electromagnetic interference, enhancing current-handling capability and signal integrity while maintaining efficient voltage conversion.

Implementation Method 1

a parallel-plate capacitor formed by an insulating layer and two conductive layers of the stack arranged on opposite sides of the insulating layer

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

the first metal plane and the second metal plane are arranged between the top conductive layer and the two signal layers, thereby electrically shielding the first and the second signal layer from the top conductive layer

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Implementation Method 3

a plurality of via holes configured to electrically connect the top conductive layer with the first metal plane and the second metal plane

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentEP4651635A1PCB layer stack-up and floor planning
Publication Date: 2025.11.19 RIMAC ENERGY LLC
  • EP4651635A1 patent drawingFigure 1
  • EP4651635A1 patent drawingFigure 2
  • EP4651635A1 patent drawing

AI summary

A voltage converting circuit comprises a multi-layer printed-circuit-board stack having an input terminal and a reference terminal, first and second switching elements connected to each other at an output terminal and a parallel-plate capacitor connected with the first and the second switching elements; the stack comprises a top conductive layer provided with said input, reference and output terminals and with a plurality of power-conducting traces, a first and a second metal plane forming said electrodes of the parallel-plate capacitor, a first and a second signal layer having first and second signal-routing traces, wherein the first and the second metal plane are arranged between the top conductive layer and two signal layers, and wherein the top conductive layer and the first metal plane are separated from each other by an insulating layer of the stack only.