Printed Wiring Board Staggered Layer Design for Size Reduction
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Solution Overview
Problem
Conventional printed wiring boards with T-branching bus wirings are large in size due to parallel arrangement of multiple wirings, leading to increased size of electronic devices.
Innovation Solution
A printed wiring board with multiple layers and via conductors that bridge these layers, allowing conductor patterns on different layers to overlap and extend in a staggered manner, reducing the overall size by minimizing wiring length and preventing short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wirings are arranged in parallel in the width direction, then signal transmission between elements is achieved, but the printed wiring board size increases
Solution Approach 1:
The patent transitions from two-dimensional parallel wiring arrangement to three-dimensional staggered arrangement across multiple layers. Conductor patterns on different layers are positioned to overlap when viewed from above, with via conductors connecting corresponding patterns across layers. This vertical stacking approach reduces the horizontal footprint of the printed wiring board while maintaining effective signal transmission paths between elements.
2Length of stationary object
If conductor patterns on different layers are positioned to overlap, then wiring length is minimized, but short-circuit risk increases
Solution Approach 1:
The patent divides the conductor connection path into separate segments on different layers, with via conductors acting as connection points between layers. By positioning conductor patterns to overlap rather than directly contact, and using vias to bridge corresponding patterns on adjacent layers, the design minimizes wiring length while preventing short-circuits through spatial separation of conductive elements.
Data Source
AI summary
A printed wiring board includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings each include a first via conductor disposed outside a first region, a second region, and a third region in a plan view, and a first conductor pattern extending from the first via conductor to the first region. The plurality of second wirings each include a second via conductor disposed outside the first region, the second region, and the third region, and a second conductor pattern extending from the second via conductor to the first region. A fourth region overlaps with a fifth region in the plan view, the fourth region being a region in which a plurality of first conductor patterns are disposed, the fifth region being a region in which a plurality of second conductor patterns are disposed.