Multilayer PCB Sublaminates Mitigating Swiss Cheese Effect
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Solution Overview
Problem
The 'swiss cheese effect' in high-current circuit boards, caused by numerous holes combining to form larger openings, limits the real estate available for conductive vias, making it difficult to support high-current devices by restricting the amount of current that can be carried.
Innovation Solution
The design involves a circuit board with two unique sublaminates, one containing ground layers and signal layers, and the other containing power layers and signal layers, stacked such that they mirror each other across a symmetry axis, reducing the number and length of vias needed to connect internal planes to conductive contacts and traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous holes are used to connect internal planes and layers, then connectivity is achieved, but the real estate available for conductive vias is reduced due to the swiss cheese effect
Solution Approach 1:
The circuit board is divided into two distinct sublaminates: a first sublaminate containing ground layers and signal layers, and a second sublaminate containing power layers and signal layers. This segmentation allows each sublaminate to be optimized independently, with the first sublaminate providing ground connectivity and the second sublaminate providing power connectivity, thereby reducing the need for numerous overlapping holes that cause the swiss cheese effect.
Solution Approach 2:
The invention introduces a vertical stacking dimension by laminating multiple sublaminates on top of each other. By distributing ground layers, power layers, and signal layers across different vertical levels (z-dimension), the design reduces the need for numerous holes at the same horizontal plane, thereby mitigating the swiss cheese effect while maintaining connectivity.
2Ease of manufacture
If holes are combined to form larger openings, then manufacturing is simplified, but the current carrying capacity is reduced
Solution Approach 1:
Instead of creating large combined openings that reduce current carrying capacity, the invention segments the connectivity function across multiple separate layers. Each sublaminate maintains its own set of holes and conductive paths, allowing current to flow through multiple smaller, distributed pathways rather than fewer large openings, thereby preserving current carrying capacity while simplifying manufacturing.
Solution Approach 2:
The invention merges the connectivity functions of ground and power planes into separate sublaminates that are laminated together. This combining approach allows the circuit board to achieve both ground connectivity and power connectivity simultaneously through the stacked structure, reducing the need for additional holes that would otherwise be required to connect both functions through a single substrate.
3Quantity of substance
If more conductive vias are added to support high-current devices, then current carrying capacity increases, but the swiss cheese effect worsens
Solution Approach 1:
The invention segments high-current connectivity into dedicated power layers within the second sublaminate, separate from ground layers in the first sublaminate. This segmentation allows conductive vias to be concentrated in specific regions where high current is needed, rather than distributed throughout the entire board, thereby increasing current carrying capacity without uniformly increasing via density and worsening the swiss cheese effect.
Solution Approach 2:
The invention applies local quality by providing high-density conductive vias and thick copper traces specifically in the power layers of the second sublaminate where high-current devices are mounted, while the ground layers in the first sublaminate use a different via density optimized for their function. This localized optimization allows high current carrying capacity where needed without unnecessarily increasing overall via density.
Data Source
AI summary
A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.