PCB Terminal Pitch Layout for SoC Routing and Package Area
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Solution Overview
Problem
The challenge of routing traces between vias on a PCB is exacerbated when the ball pitch of a system-on-chip (SoC) is increased to match the memory package pitch, leading to increased package area without a significant cost increase.
Innovation Solution
Implementing a method that uses optimized pitch configurations for both terminals and pads on the PCB, with different pitch values in orthogonal directions to allow space for signal lines and vias, minimizing package area without increasing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the ball pitch of the SoC package is increased to match the memory package pitch, then the routing of traces between vias becomes easier, but the package area of the SoC will be greatly increased
Solution Approach 1:
The patent applies different pitch values to different regions of the terminal array. Specifically, it uses a first pitch value for terminals in a first region and a second pitch value for terminals in a second region, where the pitch values differ. This local differentiation allows optimized routing in specific areas while maintaining compact overall package dimensions, resolving the contradiction between routing ease and package area minimization.
Solution Approach 2:
The patent changes the pitch parameter from being uniform across all terminals to being variable across different regions. By setting different pitch values (first pitch and second pitch) for different terminal regions, the invention enables both easier trace routing in regions with larger pitch and compact package area through regions with smaller pitch, thus resolving the technical contradiction.
2Quantity of substance
If a large number of vias are arranged in an SoC installation region on the PCB, then more connections can be made, but it becomes difficult to route traces between these vias
Solution Approach 1:
The patent segments the terminal array into multiple regions (first region and second region) with different pitch characteristics. This segmentation allows dense connections in regions where small pitch is used while providing routing space in regions where large pitch is used, thereby accommodating both high connection density and trace routing requirements without contradiction.
Solution Approach 2:
Different regions of the terminal array are assigned different pitch values according to their specific functional requirements. Regions requiring high connection density use smaller pitch, while regions requiring trace routing space use larger pitch. This local optimization resolves the contradiction between maximizing connections and maintaining routing ease.
Data Source
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AI summary
A method of using optimized pitch for installing a processing circuit (110) at a printed circuit board (PCB) (100B) and associated apparatus are provided. The method may include: providing a set of first terminals (111_1) on a predetermined surface (110S) of a package (110P) of the processing circuit, the set of first terminals corresponding to a set of first pads (101_1) within a first sub-region (610) of a predetermined installation region (201) of the PCB; and providing a set of second terminals (111_2) on the predetermined surface of the package of the processing circuit, the set of second terminals corresponding to a set of second pads (101_2) within a second sub-region (620) of the predetermined installation region, where a pitch (X_Pitch1, Y_Pitch1) of the first terminals and a pitch (X_Pitch2, Y_Pitch2) of the second terminals along a predetermined direction are equal to a first and a second predetermined values, respectively.