PCB In-Circuit Test Pad Via Offset Design

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Solution Overview

Problem

In-circuit tests for printed circuit boards often produce inaccurate results due to the recessed center of the test pad over a via, leading to increased resistance and unreliable data, and the soldermask can seep into the via, affecting probe contact.

Innovation Solution

An in-circuit test structure where the center of the via deviates from the center of the test pad, with a conducting layer on the via's inner wall and the via filled with soldermask, to improve accuracy and reliability by reducing the impact of the via on the test pad and preventing oxidation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the center of the test pad is located right above the via with the center part recessing toward the via, then the test pad can cover the via, but the thickness and electrical conductivity of the center part of the test pad are reduced

Engineering Contradiction:
Improvetest data accuracyVSAvoidtest pad thickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by deliberately offsetting the via center from the test pad center. The via is positioned at a specific distance from the test pad center, creating an asymmetric configuration that prevents the via from causing thickness reduction and resistance increase in the test pad center area, thereby resolving the contradiction between covering the via and maintaining pad quality.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If the via is soldermask plugged to prevent oxidation and short circuits, then electrical reliability is improved, but soldermask may seep into the via from the soldermask-plugged side affecting probe contact

Engineering Contradiction:
Improveoxidation preventionVSAvoidsoldermask seepage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the harmful effect by separating the soldermask filling function from the via structure. Instead of filling the via with soldermask, the patent uses a conducting layer that extends from the via inner wall to the test pad, eliminating the soldermask seepage problem while maintaining oxidation prevention through the via structure design.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If the via center is aligned with the test pad center, then the structure is simple and easy to manufacture, but the test probe contact resistance increases and test accuracy decreases

Engineering Contradiction:
Improvevia and test pad alignmentVSAvoidtest data accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent deliberately introduces asymmetry by positioning the via center at a specific distance from the test pad center. This asymmetric arrangement ensures that the test probe contacts the test pad at an optimal point away from the via, reducing contact resistance and improving measurement accuracy while maintaining manufacturing simplicity through standardized positioning techniques.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS9835684B2In-circuit test structure for printed circuit board
Publication Date: 2017.12.05 NVIDIA CORP
  • US9835684B2 patent drawing
  • US9835684B2 patent drawing
  • US9835684B2 patent drawing

AI summary

A printed circuit board, an in-circuit test structure and a method for producing the in-circuit test structure thereof are disclosed. The in-circuit test structure comprises a via and a test pad. The via passes through the printed circuit board for communicating with an electrical device to be tested on the printed circuit board. The test pad is formed on an upper surface of the printed circuit board and covering the via, wherein a center of the via deviates from a center of the test pad. In the in-circuit test, the accuracy of the test data can be improved by means of the in-circuit test structure provided by the present invention, and thus the reliability of the test result is ensured. Also, the test efficiency of the in-circuit test is improved.