PCB Trace Impedance Control for Memory Module Loading
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Solution Overview
Problem
Impedance mismatch between segments of a memory system's conductive traces in a daisy chain topology occurs due to changes in load when memory modules are populated, leading to unwanted reflections and noise.
Innovation Solution
A multi-layer printed circuit board with a ground reference, memory controller, and memory module connectors, where a metal element is aligned with signal conductors and controlled by a relay to adjust impedance in response to memory module installation, reducing impedance mismatch between segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same etch design is used throughout the memory system, then manufacturing complexity is reduced and ease of manufacture is improved, but impedance mismatch occurs when memory modules are populated, causing reflections and noise
Solution Approach 1:
The patent applies local quality by making specific segments of the conductive trace have different cross-sectional dimensions than other segments. The first segment has different dimensions to compensate for the loading effect caused by populated memory modules, while other segments maintain the standard etch design. This localized modification resolves the impedance mismatch problem without requiring a complete redesign of the entire trace system.
Solution Approach 2:
The patent changes the physical parameters (cross-sectional dimensions) of specific trace segments to alter their electrical characteristics. By adjusting the width, thickness, or other dimensional parameters of the first segment, the characteristic impedance is modified to compensate for the loading effect, thereby maintaining signal integrity despite the presence of populated memory modules.
2Adaptability or versatility
If memory modules are populated in memory module connectors, then the functionality and capacity of the memory system are improved, but the load changes cause characteristic impedance to change, leading to impedance mismatch
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the expected loading effect of populated memory modules through modified trace dimensions. The first segment is designed with different cross-sectional dimensions before the memory modules are installed, specifically to counteract the impedance-lowering effect that will occur when modules are populated. This preemptive design approach maintains impedance matching without requiring dynamic adjustment.
3Reliability
If the cross-sectional dimensions of conductive traces are modified in specific segments, then impedance matching is improved and reflections are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent limits the precision requirements to only specific local areas rather than the entire trace system. Only the first segment requires modified cross-sectional dimensions with corresponding precision controls, while other segments can be manufactured using standard tolerances. This localized approach reduces the overall manufacturing complexity while achieving the necessary impedance matching.
Data Source
AI summary
A control circuit is provided on a printed circuit board to detect the presence of a memory module installed in at least one of a plurality of memory module connectors, wherein installation of the memory module is known to cause impedance to decrease in a segment of a daisy chain memory circuit. The impedance of a first signal conductor of the daisy chain memory circuit is automatically altered to reduce a mismatch in impedance between the first signal conductor and the segment in response to detecting the presence of the memory module in the connector. A metal element is incorporated into the printed circuit board a spaced distance from the first signal conductor, and the control circuit may selectively activate one or more relays to cause the metal element to function as either a floating trace or a ground reference.