PCB Trace Segmentation for Individual Chip Enable Signals
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Solution Overview
Problem
Semiconductor packages face challenges in efficiently providing a single chip enable (CE) signal during electrical testing while also allowing individual CE signals to each memory die during normal operations, due to limited space on the test pad matrix and the need for redesign of test sockets and packaging.
Innovation Solution
A semiconductor package design that uses a single CE signal during electrical testing, with electrical traces initially shorted together from the memory test pad matrix, allowing individual CE signals to be communicated separately to each memory die after testing, either by severing the traces or using a conductive element to isolate them, enabling efficient power management during normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single CE signal is used during electrical testing, then testing efficiency is improved, but individual control of memory dies during normal operations cannot be achieved
Solution Approach 1:
The electrical traces are segmented into multiple separate traces after testing, allowing a single CE signal during testing to be divided into individual CE signals for each memory die during normal operations. This segmentation enables both testing efficiency and individual control capability.
Solution Approach 2:
The electrical connection configuration is made dynamic by allowing traces to be shorted together during testing and then separated during normal operations. The system transitions from a connected state during testing to a separated state during operation, adapting the signal distribution based on the operational mode.
2Adaptability or versatility
If separate CE signals are provided for each memory die, then individual control is enabled, but device complexity and space requirements increase
Solution Approach 1:
The electrical traces are pre-configured to be shorted together during the testing phase, eliminating the need for separate CE signals during testing. The separation of traces occurs only after testing is complete, reducing complexity during the critical testing phase.
Solution Approach 2:
The electrical traces serve multiple functions: they act as a single shared path during testing and as separate individual paths during normal operations. This multi-functionality reduces the overall complexity by using the same physical infrastructure for both modes.
3Adaptability or versatility
If test sockets and packaging are redesigned to support individual CE signals, then individual control is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The electrical traces are merged into a single shorted path during testing, eliminating the need for separate test sockets and packaging modifications. The traces are only separated after testing, avoiding manufacturing complexity during the production process.
Data Source
AI summary
A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.