PCB Transposition Channel Routing for Crosstalk Reduction
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Solution Overview
Problem
Conventional escape routing techniques for printed circuit boards (PCBs) implementing high data rate channels, such as DDR5 memory modules, face challenges with increased package size, channel bandwidth, and decreased via and pad spacing, leading to signal degradation due to crosstalk and noise interference.
Innovation Solution
The implementation of transposition channel routing techniques, which involve repositioning signal lines using micro-vias from one routing layer to another, effectively reducing crosstalk by altering the phase relationship and partially canceling coupled signals, thereby improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional escape routing techniques are used, then the routing structure is simple, but signal quality deteriorates due to crosstalk and noise interference
Solution Approach 1:
The patent applies dimensionality change by transitioning signal routes from a two-dimensional plane to a three-dimensional space using multiple PCB layers. Signal lines are routed across different layers (e.g., from layer 1 to layer 3) to physically separate them from adjacent signal lines that would otherwise be in close proximity on the same layer, thereby reducing crosstalk and noise interference while maintaining routing manageability
Solution Approach 2:
The patent uses vias as intermediary elements to connect signal lines across different PCB layers. These vias serve as mediators that enable the signal to transition between layers, allowing the routing structure to achieve better signal quality through spatial separation while maintaining the electrical connection. The via acts as the intermediary component that resolves the conflict between simple routing and signal quality
2Area of stationary object
If via and pad spacing is decreased to reduce package size, then package size is reduced, but signal degradation increases due to increased crosstalk
Solution Approach 1:
The patent resolves the spacing contradiction by utilizing the vertical dimension (z-axis) through multiple PCB layers. Instead of increasing horizontal spacing between vias and pads on the same layer, the routing transitions to adjacent layers, effectively using the third dimension to achieve signal separation. This allows compact package design with reduced via and pad spacing while maintaining signal quality through inter-layer routing separation
Solution Approach 2:
The patent segments the signal routing path into multiple segments across different PCB layers. By dividing the continuous routing path into discrete segments on different layers (e.g., segment on layer 1, transition via, segment on layer 3), the design can use smaller via and pad spacing on each individual layer while the overall signal path benefits from reduced crosstalk due to layer separation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces crosstalk and enhances signal quality, achieving improved signal-to-noise ratio and increased reliability for high data rate applications by canceling out interference along the escape route.
Implementation Method 1
reduces crosstalk and realizes significant signal quality improvement... partially cancelling coupled signal lines in a channel
Data Source
AI summary
Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.