PCB Embedded Venting Channels for False Tamper Prevention
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Solution Overview
Problem
Sealed cryptographic modules in FIPS-4 compliant systems are susceptible to false tamper detection due to pressure differences between the internal and external environments, which can lead to mechanical deformation and sensor failure.
Innovation Solution
An integrated venting system is implemented in the printed circuit board (PCB) with at least three interconnected access points (VIAs) and a channel spanning through them, maintaining an isobaric environment and preventing tampering by positioning these access points strategically relative to the enclosure and embedded logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cryptographic module is sealed within an enclosure to prevent tampering, then security protection is improved, but pressure differences cause mechanical deformation and false tamper detection
Solution Approach 1:
A pressure equalization channel is created as an intermediary pathway between the sealed enclosure interior and exterior. This channel allows pressure to equalize on both sides of the enclosure, eliminating the harmful pressure differential that causes mechanical deformation and false tamper detection, while maintaining the sealed protective barrier.
Solution Approach 2:
The enclosure structure is segmented to include a dedicated pressure equalization pathway separate from the security sealing. The sealant material is applied in specific segments around the PCB perimeter, with controlled gaps or channels that allow pressure equalization without compromising the overall security seal.
2Reliability
If the enclosure is completely sealed to detect tampering, then tamper detection capability is improved, but false detection occurs due to pressure changes
Solution Approach 1:
The pressure equalization channel acts as a mediator that eliminates false pressure-based tamper signals. By allowing pressure to equalize through the channel, the tamper detection sensor no longer receives false readings from pressure differentials, improving detection accuracy while maintaining the sealed enclosure's security function.
Solution Approach 2:
The pressure parameter within the enclosure is changed from a sealed, pressurized state to an isobaric, equalized state through the venting channel. This parameter change eliminates the source of false tamper detection signals while preserving the physical security barrier.
3Reliability
If the enclosure is sealed to protect cryptographic logic, then security is improved, but mechanical deformation occurs due to pressure differential
Solution Approach 1:
The pressure equalization channel serves as a mediator that eliminates the pressure differential causing mechanical deformation. By allowing pressure to equalize between the enclosure interior and exterior, the structural integrity of the sealed enclosure and its components is maintained while preserving the security protection.
Solution Approach 2:
The pressure equalization channel provides beforehand cushioning by preventing pressure differential buildup before it can cause mechanical deformation. The channel is designed to equalize pressure proactively, cushioning the enclosure structure against potential deformation forces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The venting system effectively mitigates false tamper detection by maintaining equilibrium pressure, enhancing the security protocol and preventing mechanical deformation of sensors, thus ensuring the integrity of the cryptographic module.
Implementation Method 1
The integrated venting system functions to maintain an isobaric environment between a portion of the PCB that is housed within the enclosure and atmospheric pressure
Data Source
AI summary
The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.