Multilayer PCB Via Structure for Current Distribution
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Solution Overview
Problem
Conventional via structures in printed circuit boards (PCBs) face limitations in achieving reliable connections between conductor layers due to high impedance and large current density, leading to increased resistance and temperature issues, which can shorten the lifespan of PCBs.
Innovation Solution
A novel via structure is introduced, where vias are arranged in overlapping regions with an in-out ratio of (A+1):A, allowing each row of vias to puncture through at least one current input and one current output layer, and some rows puncture through all or a part of the conductor layers, optimizing current flow and reducing resistance without increasing the number of vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of vias is increased to realize reliable connections between conductor layers, then connection reliability is improved, but the area of PCB is excessively occupied and manufacturing complexity increases
Solution Approach 1:
The patent transitions from conventional 2D via arrangements to a 3D stacked via structure where vias are arranged in multiple rows and columns with different penetration depths. This dimensional change allows multiple vias to share the same footprint area, significantly reducing the PCB area occupied while maintaining reliable connections between conductor layers through vertical stacking.
Solution Approach 2:
The patent implements nested via structures where inner vias are positioned within the footprint of outer vias, creating a nested arrangement. This nesting allows multiple conductor layers to be connected through shared via locations, reducing the total area required for via connections while maintaining connection reliability across multiple layers.
2Reliability
If via walls are made thinner to reduce via size, then via impedance increases, but via current carrying capacity decreases and temperature increases
Solution Approach 1:
The patent divides the via current path into multiple segments by creating stacked via structures with multiple rows and columns. Each via in the stack carries a portion of the total current, effectively segmenting the current load. This segmentation allows thinner via walls to be used while maintaining adequate current carrying capacity and controlling temperature rise.
Solution Approach 2:
The patent combines multiple vias into a stacked via structure where multiple via holes share the same footprint area. By merging the function of multiple vias into a compact stacked arrangement, the patent achieves both low impedance (through multiple parallel current paths) and reduced temperature (through distributed current loading across multiple via walls).
Data Source
AI summary
The present disclosure provides a via structure and a multilayer circuit board including the via structure. The via structure is provided in three or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and including at least one current input layer and at least one current output layer; wherein the via structure includes a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, and a part of the rows of vias puncture through all of the conductor layers, and the other part of the rows of vias puncture through a part of the conductor layers. By using the via structure in the present disclosure, the vias are subject to even temperature and thus the lifetime of the circuit board is extended.