PCB Via Current Distribution via Segmented Planes
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Solution Overview
Problem
In densely packed printed circuit boards, the uniform distribution of power supply vias to prevent overheating and damage from current concentration is challenging, as equal impedance requirements conflict with optimizing component mounting density.
Innovation Solution
The proposed solution involves a multi-level plane structure with vias strategically located in different portions of voltage supply regions, including a first portion for the power supply pin and separate second and third portions for other vias, which are electrically insulated from signal pins and wiring, to manage impedance and current distribution effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vias are densely located around the power supply pin to reduce board size, then component mounting density is improved, but current concentration causes overheating and damage to surrounding components
Solution Approach 1:
The patent segments the voltage supply region into multiple portions (first, second, and third portions) and distributes vias across different portions rather than concentrating them in one location. This segmentation reduces current concentration on any single via while maintaining adequate power supply to densely mounted components.
Solution Approach 2:
The patent applies different electrical characteristics to different portions of the voltage supply region. The first portion is electrically connected to the power supply pin with controlled impedance, while the second and third portions are electrically insulated from signal pins and wiring. This local differentiation allows optimized current distribution and reduces harmful current concentration.
2Reliability
If vias are located at equal distance from the power supply pin to equalize impedance, then current distribution is improved, but optimization of component mounting density is hindered
Solution Approach 1:
The voltage supply region is divided into multiple portions that can be independently configured. Vias can be placed in the second and third portions which are electrically insulated from signal wiring, allowing flexible positioning that optimizes both current distribution and component mounting density without requiring uniform spacing.
Solution Approach 2:
The patent utilizes multiple layers (first layer and second layer) to distribute vias in three-dimensional space. By placing vias on different layers and in different portions, the design achieves balanced current distribution while providing flexibility for component placement optimization in the planar dimension.
3Power
If vias are placed closer to the power supply pin to reduce path impedance, then power delivery is improved, but current stress on the path increases causing overheat
Solution Approach 1:
The patent segments the via placement into different portions: the first portion near the power supply pin with controlled impedance for efficient power delivery, and the second and third portions electrically insulated from signal wiring to reduce current stress and heating on critical paths.
Solution Approach 2:
The patent introduces electrically insulated portions (second and third portions) as intermediaries between the power supply pin and signal wiring. These portions act as buffers that reduce direct current stress on critical signal paths while maintaining power delivery efficiency through the first portion.
Data Source
AI summary
Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.