PCB Via Fill Dimple Suppression via Preliminary Conductor Pattern
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Solution Overview
Problem
The semi-additive process (SAP) and modified semi-additive process (MSAP) methods for forming circuits on printed circuit boards often result in dimples due to plating deviations during via fill plating, leading to reduced flatness and manufacturing yield.
Innovation Solution
A printed circuit board design where a conductor pattern is formed on the via pad within the via hole before via fill plating, using a first metal layer covering the via hole walls and exposed surfaces, and a second metal layer filling the via hole, thereby suppressing dimple formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via fill plating is performed using conventional SAP or MSAP methods, then interlayer connection is achieved, but dimples occur due to plating deviation reducing flatness and manufacturing yield
Solution Approach 1:
A conductor pattern is formed on the via pad before via fill plating is performed. This preliminary conductor pattern serves as a base that prevents plating deviation and subsequent dimple formation during the via fill plating process, thereby maintaining board flatness while achieving reliable interlayer connection
Solution Approach 2:
The conductor pattern is specifically disposed on the via pad surface within the via hole region. This localized conductor pattern provides targeted plating nucleation sites exactly where needed, preventing plating deviation at the via pad interface without affecting other areas of the board
2Reliability
If via fill plating is performed to form multilayer circuit, then interlayer connection is achieved, but manufacturing yield decreases due to dimple occurrence
Solution Approach 1:
The conductor pattern is formed in advance on the via pad before via fill plating. This preliminary structure ensures uniform plating deposition by providing a consistent base layer, thereby preventing dimple formation and improving manufacturing yield while maintaining interlayer connection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the flatness of the printed circuit board and enhances manufacturing yield by preventing dimple occurrence during via fill plating, ensuring a more reliable interlayer connection.
Implementation Method 1
a first metal layer covering at least a portion of each of a wall surface of the via hole, the exposed upper surface of the via pad, and the conductor pattern
Implementation Method 2
a second metal layer disposed on the first metal layer and disposed in at least a portion of the via hole
Data Source
AI summary
A printed circuit board includes: a first insulating layer; a via pad disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and having a via hole exposing at least a portion of an upper surface of the via pad; a conductor pattern disposed on the exposed upper surface of the via pad; and a via including a first metal layer covering at least a portion of each of a wall surface of the via hole, the exposed upper surface of the via pad, and the conductor pattern, and a second metal layer disposed on the first metal layer and disposed in at least a portion of the via hole.