PCB Via Grouping for Thermal Management
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Solution Overview
Problem
Printed circuit boards experience overheating issues due to varying current distribution across vias, with those closer to the power supply or load receiving excessive current, leading to potential thermal problems.
Innovation Solution
The design incorporates a power rail architecture with multiple power layers and strategically arranged via groups, where each row of vias is electrically connected to a specific number of power layers based on a calculated minimum and maximum connection rule, minimizing excessive current exposure and reducing overheating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If vias are arranged in an array and electrically connected to power layers, then power transmission capability is improved, but vias close to power supply or load units are subjected to excessive current causing over-temperature
Solution Approach 1:
The patent applies local quality by differentiating the electrical connection configuration of vias based on their position. Vias are divided into different groups (first via group and second via group) with different connection patterns to power layers. Specifically, vias in the first via group are connected to fewer power layers compared to vias in the second via group, creating localized variations in current distribution that prevent overheating in high-current regions while maintaining power transmission capability.
Solution Approach 2:
The patent segments the via array into multiple groups (first via group and second via group) with different electrical connection characteristics. This segmentation allows different portions of the via array to handle different current loads appropriately, with the first via group handling lower current and the second via group handling higher current, thereby resolving the contradiction between power transmission and temperature control.
2Power
If multiple power layers are used to transmit current, then power transmission efficiency is improved, but current distribution across vias becomes uneven causing overheating
Solution Approach 1:
The patent implements local quality by creating spatially varying electrical connection patterns between vias and power layers. The first via group has a different connection configuration (connected to fewer power layers) compared to the second via group (connected to more power layers). This localized differentiation ensures that vias experiencing higher current loads are connected to more power layers for better heat dissipation, while vias with lower current loads have simpler connections, thus maintaining both power transmission efficiency and thermal reliability.
3Power
If vias are closely arranged to increase power capacity, then power transmission capability is improved, but heat concentration increases leading to over-temperature
Solution Approach 1:
The patent applies local quality by assigning different electrical connection patterns to different via groups based on their thermal environment. Vias in the first via group, which are more susceptible to thermal stress, are connected to fewer power layers to reduce current density. Vias in the second via group, which can handle higher thermal loads, are connected to more power layers to maximize power transmission. This localized adaptation resolves the contradiction between power capacity and thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces overheating by distributing current more evenly across the vias, preventing thermal issues and enhancing power transmission efficiency.
Implementation Method 1
The N power layers transmit a current towards a first direction away from the first side of the printed circuit board
Implementation Method 2
Each row of the M rows of vias is electrically connected to a first layer of the N power layers. A Pth row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively
Data Source
AI summary
A printed circuit board is provided. The printed circuit board includes N power layers and a first via group. The N power layers are arranged in parallel and spaced from each other. The first via group includes M rows of vias which are disposed through the N power layers, where N and M are positive integers greater than 0. Each row of the M rows of vias is electrically connected to the first layer of the N power layers. A Pth row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively, where Q is a smallest positive integer greater than or equal to P((N−1)/M), and P is a positive integer less than or equal to M.