PCB Via Layout for Low Current Measurement Leakage Reduction
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Solution Overview
Problem
Current methods for measuring low currents on printed circuit boards (PCBs) face challenges due to current leakage and dielectric absorption, which are difficult to discriminate from the signal being measured, and existing techniques like trenching require significant PCB real estate and make the board fragile.
Innovation Solution
The implementation of a printed circuit board design that includes a node with multiple rows of vias configured to establish current pathways away from the node, with guard planes in adjacent layers to reduce leakage current, and optionally features a cavity for accessible measurement terminals, allowing for more efficient low current measurement without the need for extensive trenching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If trenches are made around the measurement node to reduce leakage current, then leakage current is reduced, but PCB real estate is consumed and the board becomes fragile
Solution Approach 1:
The patent transitions from two-dimensional surface trenching to three-dimensional via-based current pathways through multiple PCB layers. By utilizing vertical via structures and distributing current paths across multiple layers, the solution reduces leakage without requiring large surface area trenches that would compromise PCB strength.
Solution Approach 2:
The patent divides the current pathways into multiple segmented via rows distributed across different PCB layers. Instead of a single continuous trench, the current is guided through multiple discrete via segments that collectively block leakage paths while preserving PCB structural integrity.
2Measurement precision
If trenches are made around the measurement node to reduce leakage current, then leakage current is reduced, but the PCB real estate is consumed
Solution Approach 1:
The patent moves the leakage blocking function from the two-dimensional surface plane to the third dimension by using vias that extend through multiple PCB layers. This vertical approach achieves effective leakage reduction without consuming valuable horizontal PCB real estate.
Solution Approach 2:
The patent uses arrays of vias (which are essentially porous or hollow conductive structures) to create current pathways. These via structures provide effective leakage blocking through their geometric configuration across multiple layers while occupying minimal PCB surface area.
3Measurement precision
If guard planes are added to reduce leakage current, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The via structures serve multiple functions simultaneously: they provide mechanical support, establish electrical connections between layers, and create current pathways that block leakage. This multi-functionality reduces the need for additional dedicated guard structures, thereby limiting complexity increase.
Solution Approach 2:
The patent combines the functions of structural support, electrical connection, and leakage blocking into a single via structure. By merging these functions, the design avoids adding separate guard planes or structures, thus limiting the increase in device complexity while still achieving leakage reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces leakage current at the measurement node, improving the accuracy of low current measurements and maintaining PCB integrity by minimizing the impact of dielectric absorption and current leakage, while allowing for precise current measurement across a range including femto-amperes.
Implementation Method 1
a plurality of rows of vias that may be configured to establish a plurality of current pathways away from the node
Implementation Method 2
a second layer of the plurality of layers may include a guard plane. The guard plane may be configured to reduce leakage current at the node
Data Source
AI summary
System and methods for use and fabrication of a printed circuit board (PCB). The PCB may include a node and a plurality of rows of vias that may be configured to establish a plurality of current pathways away from the node. The node may be a sensitive node and the plurality of current pathways may reduce leakage current at the node responsive to a signal applied to the node. Each row of the plurality of rows of vias may be offset with respect to adjacent rows of vias in a horizontal plane of the PCB. The PCB may have multiple layers and the node may be on an exterior surface layer or an interior layer. The vias may be mirco-vias, buried-vias, or through-vias.