PCB Via Layout for Memory Interface Timing and Frequency Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic modules face challenges in achieving high communication speeds due to variations in signal arrival times and frequency loss in wiring, particularly in memory interfaces, which hinder the speedup of clock signals and reduce voltage noise margins.
Innovation Solution
The implementation of a wiring structure with overlapping and intersecting via groups connected to terminal groups on a multi-layer printed wiring board, utilizing meander wiring to equalize signal line lengths and reduce frequency loss, thereby optimizing signal transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to speed up communication, then the communication speed is improved, but the variation in signal arrival time increases and voltage noise margin decreases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional via arrangements. By stacking vias in multiple layers (first via group, second via group, third via group arranged in different directions and layers), the signal path is optimized in the vertical dimension, reducing overall path length and equalizing arrival times across different signal lines while maintaining high communication speeds
Solution Approach 2:
The via connection structure is divided into multiple independent via groups (first via group connected to first terminal group, second via group connected to second terminal group, etc.). Each via group is arranged independently with specific orientations, allowing separate optimization of each signal path to achieve equalized arrival times and reduced variation
2Device complexity
If conventional planar wiring is used, then the device complexity is low, but the signal line length variation is large causing timing skew
Solution Approach 1:
The patent employs multi-layer via arrangements where vias are stacked in vertical layers rather than arranged in a single plane. The first via group, second via group, and third via group are positioned at different vertical levels and oriented in different directions, creating a three-dimensional wiring structure that equalizes signal paths without excessive planar complexity
Solution Approach 2:
Different via groups are arranged with different orientations and positions to compensate for asymmetric signal path lengths. The first via group is arranged in a first direction, the second via group in a second direction, and the third via group in a third direction, creating an asymmetric but balanced overall structure that equalizes arrival times
Data Source
AI summary
In an electronic module, a first via connected to a first terminal of a first terminal group of a first semiconductor element and a second via connected to a second terminal of the first terminal group are arranged in a first direction. A fourth via adjacent to a third via is arranged in a second direction intersecting the first direction. A virtual straight line connecting the first via and the second via passes between the third via and the fourth via. A first wiring connecting the first via and the fifth via connected to the fifth terminal of the third terminal group of the second semiconductor element and a second wiring connecting the second via and the sixth via connected to the sixth terminal of the third terminal group pass between the third via and the fourth via.