PCB Via Routing for Memory Bus Congestion
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Solution Overview
Problem
As printed circuit boards increase in size and complexity, routing congestion occurs due to long and complex traces connecting signal pins, leading to degraded signal quality and slower operation speeds, particularly in multiplex bus configurations where traces must connect disparate signal pins while avoiding overlap and ensuring correct signal transmission order.
Innovation Solution
The implementation of a printed circuit board design that uses vias to connect signal pins directly across surfaces, reducing trace length and congestion by associating each signal pin of the memory controller with corresponding pins on memory devices, and organizing pins into buses for efficient signal transmission without compromising the integrity of multiplex buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traces are laid out around the layout of signal pins and other traces to connect origin pin to destination pin, then routing flexibility is improved, but trace length increases and signal quality degrades
Solution Approach 1:
The patent introduces a via layer (third dimension) to connect signal pins between different surfaces of the PCB. Instead of routing traces only on the surface around other pins and traces, the invention uses vias to create direct vertical connections through the board, transforming a 2D routing problem into a 3D solution that dramatically shortens trace length while maintaining routing flexibility.
2Adaptability or versatility
If additional layers are added to the printed circuit board to accommodate crossing traces, then routing capacity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent utilizes the via layer (additional dimension) to resolve trace crossings without requiring additional signal routing layers. By connecting pins vertically through the board using vias, the invention allows traces on different surfaces to cross without interfering with each other, thereby increasing routing capacity while avoiding the need to add more complex multi-layer signal routing.
3Adaptability or versatility
If traces are made long and indirect to connect signal pins on opposite surfaces, then pin placement flexibility is improved, but operation speed decreases due to signal degradation
Solution Approach 1:
The patent uses vias to create direct vertical pathways through the PCB, allowing signal pins on opposite surfaces to be connected with minimal trace length. This dimensional approach enables flexible pin placement on different surfaces while maintaining short signal paths, thereby preserving operation speed despite the flexibility in pin positioning.
Solution Approach 2:
The via acts as an intermediary element that facilitates direct connection between signal pins on opposite surfaces. Instead of requiring long surface traces to reach across the board, the via provides a direct conductive pathway through the board substrate, enabling short connection lengths while maintaining pin placement flexibility.
4Adaptability or versatility
If multiple stubs are present in traces connecting memory controller to memory devices, then routing adaptability is improved, but signal quality and operation speed degrade
Solution Approach 1:
The patent employs vias to create direct vertical connections that eliminate or minimize stubs in the signal path. By routing signals through the via layer rather than along the surface around other components, the invention achieves routing adaptability while maintaining clean, stub-free signal paths that preserve signal quality and operation speed.
Data Source
AI summary
A printed circuit board having reduced routing congestion and a method of connecting components on a printed circuit board is disclosed. In one embodiment, a printed circuit board includes a memory controller and memory device. Signal pins of the memory controller and the first memory device are organized into one or more buses based on common functionality, which may be address, data, or command, or any combination thereof. The printed circuit board further includes a plurality of traces connecting each of the signal pins of the memory controller to any one the signal pins of the first memory device belonging to the same bus. The memory controller is configured to associate each one of the signal pins of the memory controller with one of the signal pins of the first memory device that are connected by a plurality of traces.