Printed Circuit Board Via Pad Width Control for 5G RF Loss
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Solution Overview
Problem
The existing printed circuit boards face challenges in miniaturization and design freedom, particularly in the 5G era, due to reduced RF performance and increased path loss, which limits the integration of active antenna systems and circuit density.
Innovation Solution
A printed circuit board design featuring via portions with pads of equal or smaller width than the via surfaces, allowing for increased separation distances and improved circuit density, along with a multilayer structure that enables flexible alignment of via parts and pads, enhancing design freedom and substrate reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the circuit line width is miniaturized to increase circuit integration density, then the circuit density is improved, but the RF performance deteriorates due to increased path loss
Solution Approach 1:
The patent transitions from planar 2D circuit routing to 3D vertical routing through stacked via portions. Multiple via portions are arranged in vertical stacks connecting different layers, enabling signals to travel through the third dimension (depth) rather than only across the surface. This dimensional change reduces the horizontal path length and associated RF losses while maintaining high circuit density.
Solution Approach 2:
The patent implements nested via structures where smaller via portions are positioned within or adjacent to larger via portions across multiple layers. The via portions are arranged in concentric or overlapping patterns vertically, creating a nested configuration that maximizes space utilization and reduces signal path length through efficient vertical stacking.
2Length of moving object
If the pad width is reduced to match the via width for miniaturization, then the circuit size is reduced, but the design freedom deteriorates
Solution Approach 1:
The pad structure is segmented into multiple via portions with different widths arranged vertically. Each via portion can have independent width dimensions, allowing the overall pad structure to be divided into functional segments. This segmentation enables miniaturization of individual via components while maintaining design flexibility through varied width configurations in different vertical layers.
Solution Approach 2:
Different via portions within the pad structure have locally optimized widths suited to their specific functions. Smaller via portions are used where space is constrained, while larger via portions are used where broader connectivity is needed. This local quality variation allows the pad to achieve miniaturization in critical areas while preserving design freedom in other areas through differentiated dimensional characteristics.
3Quantity of substance
If multiple via portions are aligned vertically to increase circuit density, then the circuit integration is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The pad structure is formed with preliminary via portions in lower layers before forming via portions in upper layers. This sequential, bottom-up formation process establishes reference structures that guide subsequent via formation. By preparing the foundation first, the manufacturing process achieves vertical alignment through cumulative precision rather than requiring simultaneous multi-layer alignment, thereby reducing overall manufacturing precision requirements.
4Length of moving object
If the via portions are made smaller for miniaturization, then the circuit pitch is reduced, but the substrate reliability deteriorates
Solution Approach 1:
Multiple via portions are merged into vertical stacks where smaller individual vias are combined to form a composite connection structure. While each individual via portion is miniaturized, the cumulative effect of multiple stacked via portions provides redundant connection paths and distributed stress relief, thereby maintaining or even improving substrate reliability despite reduced individual via dimensions.
Data Source
AI summary
A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via portion disposed in the first insulating layer; and a second via portion disposed in the second insulating layer; wherein the first via portion includes: a first via part passing through the first insulating layer; a first-first pad disposed on an upper surface of the first insulating layer and connected to an upper surface of the first via part; and a first-second pad disposed on a lower surface of the first insulating layer and connected to a lower surface of the first via part; wherein the second via portion includes: a second via part passing through the second insulating layer and having a lower surface connected to an upper surface of the first-first pad; a second pad disposed on an upper surface of the second insulating layer and connected to an upper surface of the second via part; wherein a width of the first-first pad is smaller than or equal to a width of the upper surface of the first via part; and wherein a width of the second pad is smaller than or equal to a width of the upper surface of the second via part.