PCB Via Pad Width Reduction for 5G Circuit Density
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Solution Overview
Problem
The existing printed circuit boards face challenges in miniaturization and thinning, especially in the 5G era, due to reduced design freedom and degraded RF performance caused by the pad connected to the via.
Innovation Solution
A printed circuit board structure is introduced, featuring a via portion with a first pad under the insulating layer and a second pad on the insulating layer, where the width of the first pad is less than or equal to the width of the via part, allowing for increased separation distance between via portions and improved circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pad connected to the via is used in conventional printed circuit boards, then the via can be connected to the circuit pattern, but the design freedom is significantly reduced and RF performance is degraded
Solution Approach 1:
The patent extracts the pad structure from the conventional via configuration. Instead of using a pad connected to the via, the invention uses a via portion that directly contacts the circuit pattern, eliminating the pad and its associated problems with design freedom and RF performance.
Solution Approach 2:
The patent inverts the conventional approach by making the via portion wider than the circuit pattern it contacts. This inversion allows the via to directly contact the pattern without requiring a pad, thereby improving design freedom and RF performance while maintaining electrical connection.
2Productivity
If the circuit pattern is miniaturized for 5G communication systems, then the integration density increases, but the separation distance between via portions becomes insufficient
Solution Approach 1:
The patent changes the dimensional relationship between the via portion and the circuit pattern. By making the via portion wider than the pattern in the horizontal dimension while maintaining direct contact, it enables finer circuit patterns with adequate separation distances for miniaturized 5G applications.
3Productivity
If the line width of circuits is reduced to several micrometers or less for nanometer scale integration, then the circuit integration degree increases, but the etching process causes loss of line width
Solution Approach 1:
The patent forms the via portion with a width greater than the circuit pattern before the etching process. This preliminary sizing ensures that even after etching, the via maintains sufficient width and does not cause line width loss in the fine circuit patterns.
Data Source
AI summary
A printed circuit board according to an embodiment includes an insulating layer; and a via portion disposed on the insulating layer; wherein the via portion includes: a first pad disposed under the insulating layer; a second pad disposed on the insulating layer; and a via part disposed between the first and second pads in the insulating layer; and wherein a width of the first pad is less than or equal to a width of a lower surface of the via part.


