PCB Via Placement Automation for Radiation Noise Suppression
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Solution Overview
Problem
Existing printed circuit board design methods require manual and time-consuming visual checks for determining optimal positions of additional vias to suppress radiation noise, leading to potential errors and inefficiencies, especially regarding the return current path near high-speed signal vias.
Innovation Solution
A method and apparatus that automatically specify areas for additional interlayer connection members by identifying overlapping conductive areas and determining optimal distances for via placement, reducing the need for manual intervention and minimizing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual visual check is used to determine via placement positions, then flexibility in design adjustment is maintained, but time consumption and error probability increase significantly
Solution Approach 1:
The patent replaces the manual visual inspection process with an automated computer-based calculation system. The computing device automatically calculates optimal via placement positions based on signal line configurations, eliminating the need for manual visual checks and thereby reducing both time consumption and human error while maintaining design flexibility through programmable algorithms.
Solution Approach 2:
The system enables self-service by allowing the computer to automatically determine via placement positions without requiring manual intervention. The calculation unit autonomously processes signal line data, identifies optimal via locations, and generates placement recommendations, making the design process more efficient and reliable.
2Productivity
If automated calculation method is used to determine via placement, then time consumption is reduced, but complexity of the design support system increases
Solution Approach 1:
The design support system is segmented into distinct functional units: a signal line configuration acquisition unit, a via placement calculation unit, and a result output unit. This modular segmentation allows the automated calculation to be implemented through discrete, manageable components, reducing overall system complexity while maintaining high productivity.
Solution Approach 2:
The patent introduces an intermediary calculation unit that acts as a bridge between the input signal line configuration data and the output via placement recommendations. This intermediary layer processes the data automatically using predefined algorithms, enabling fast determination without requiring complex direct manipulation by designers, thus balancing speed and system complexity.
3Object-affected harmful factors
If additional vias are arranged to suppress radiation noise, then electromagnetic wave emissions are reduced, but the number of interlayer connection members increases
Solution Approach 1:
The patent applies local quality by placing vias specifically at locations where they are most effective for suppressing radiation noise, rather than uniformly distributing them across the entire circuit board. The calculation unit identifies specific high-priority areas based on signal line configurations and places vias only in those critical zones, thereby reducing the total number of vias needed while maintaining effective noise suppression.
Solution Approach 2:
The system performs preliminary calculation to determine optimal via placement positions before actual via fabrication. By pre-calculating the exact locations where vias are needed to suppress radiation noise, the system avoids unnecessary via placements and ensures that each via serves a specific noise suppression function, thereby minimizing the total quantity of vias required.
Data Source
AI summary
A method used for supporting designing of a printed circuit board including a plurality of conductive layers having conductive areas to which a constant potential is applied, includes specifying conductive areas having a predetermined wiring from the conductive areas for each of the plurality of conductive layers, extracting areas that overlap each other in a planar view from the specified conductive areas, specifying an interlayer connection member that electrically connects at least two of the plurality of conductive layers in the extracted area, and clearly specifying an area within a predetermined distance from a center of the specified interlayer connection member and in the extracted area.