Via Hole Seed Layer Coverage in PCB Manufacturing
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Solution Overview
Problem
The existing chemical copper plating process for forming seed layers inside via holes on circuit boards results in poor coverage, leading to unplated regions and potential defects, especially when the via holes are deep.
Innovation Solution
A method involving a chemical copper plating process to form a seed layer before removing the protection film, combined with a sputtering process to enhance seed layer coverage within the via holes, including the formation of multiple seed layers with varying thicknesses and tilt angles to ensure complete coverage, and a surface treatment process to remove residues and optimize sidewall geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a sputtering process is used to form a low-thickness seed layer, then the seed layer thickness is reduced, but the coverage inside deep via holes becomes poor
Solution Approach 1:
A protection film is formed on the upper surface of the insulation layer before via hole formation. This film serves as a preliminary structure that enables selective chemical copper plating on the upper surface while preventing plating inside the via hole, allowing subsequent removal to reveal a protected upper surface with excellent seed layer coverage
Solution Approach 2:
The chemical copper plating process is applied selectively: the upper surface receives chemical plating for excellent coverage, while the inside of the via hole receives sputtering for appropriate thickness. This local differentiation of plating methods resolves the contradiction between coverage and thickness control
2Length of stationary object
If the depth of a via hole is deep, then the via hole can accommodate microcircuit structures, but the seed layer coverage toward the bottom decreases
Solution Approach 1:
The protection film is formed before via hole creation, establishing a template that guides subsequent chemical plating. This preliminary structure enables the upper surface to be plated chemically (excellent coverage) while the deep via hole interior is plated by sputtering (uniform thickness), solving the coverage problem in deep holes
Solution Approach 2:
The plating process is segmented into two distinct zones: the upper surface area plated by chemical copper plating for maximum coverage, and the via hole interior plated by sputtering for uniform thickness. This spatial segmentation allows each method to excel in its designated region
3Reliability
If a chemical copper plating process is used, then the seed layer can be formed with good coverage, but unplated regions may still occur in deep via holes
Solution Approach 1:
Different plating methods are applied to different locations: chemical copper plating is used on the upper surface where maximum coverage is needed, while sputtering is used inside the via hole where uniform thickness is critical. This local quality differentiation eliminates unplated regions while maintaining uniformity
Solution Approach 2:
The protection film is preliminarily formed to control where chemical plating occurs. After chemical plating creates excellent coverage on the upper surface, the film is removed and sputtering completes the seed layer uniformly inside the via hole, achieving both coverage and uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes unplated regions and defects within via holes, ensuring reliable conductive layer formation and facilitating the implementation of microcircuit patterns by improving seed layer coverage and reducing thickness on upper surfaces.
Implementation Method 1
forming a first seed layer covering a side wall of the via hole and an upper part surface of the protection film using a chemical copper plating process
Implementation Method 2
forming a second seed layer and a first conductive layer on the first seed layer
Data Source
AI summary
A circuit board includes a first insulation layer, a circuit wire positioned on the first insulation layer, a second insulation layer covering the circuit wire and overlapping a portion of the circuit wire, and having a via hole including a first side wall and a second side wall having different tilt angles and extending in the thickness direction of the first insulation layer, a first seed layer covering the first side wall and the second side wall of the via hole, a second seed layer positioned in the via hole and covering the first seed layer, a third seed layer positioned on an upper surface of the second insulation layer and including the same material as the second seed layer, a first conductive layer positioned on the second seed layer, and a second conductive layer positioned on the third seed layer.