Multilayer PCB Warpage Simulation for Reflow Welding Quality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in multi-layer circuit board welding is the occurrence of warpage during the reflow welding process, which can lead to internal defects and affect the yield of circuit boards, as existing methods struggle to detect and address warpage in a timely manner.
Innovation Solution
A method and device that obtain warpage data using a shadow moire technique and simulate the welding process to generate a warpage level for each region of the circuit board, allowing for the adjustment of design parameters to prevent warpage, including the use of a preset welding temperature change curve and simulation modules to process the circuit board based on the warpage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-layer circuit board is used to stack components within limited space, then component installation space is improved, but warpage occurs during reflow welding process affecting yield
Solution Approach 1:
The patent applies preliminary action by performing warpage simulation before the actual reflow welding process. The system calculates warpage data for each circuit board layer under preset temperature change curves and simulates the stacked state to generate warpage levels, allowing designers to identify and mitigate warpage risks before production, thus preventing structural damage while maintaining multi-layer stacking capability
2Measurement precision
If warpage is detected through measurement after welding, then warpage degree can be judged, but internal defects cannot be discovered in time affecting yield
Solution Approach 1:
The patent performs warpage simulation and evaluation before the actual welding process by calculating warpage data under preset temperature change curves and simulating the stacked circuit board state. This preliminary assessment allows internal defects to be identified in the design phase rather than after welding, eliminating the time loss associated with post-welding defect discovery while maintaining measurement precision through detailed warpage level analysis
3Reliability
If warpage simulation is performed for each circuit board layer, then warpage risk can be identified, but processing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the multi-layer circuit board into individual layers and calculating warpage data for each layer separately under preset temperature change curves. This segmented approach enables precise identification of warpage risks in specific layers while managing processing complexity through systematic layer-by-layer analysis rather than attempting to analyze the entire stacked structure as a single unit
Solution Approach 2:
The patent manages processing complexity by changing parameters systematically - using preset temperature change curves with characteristic points, and generating warpage levels based on simulated stacked states. These parameter standardizations allow reliable warpage risk identification across multiple layers without proportionally increasing processing complexity, as the same methodology is applied consistently to each layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the dynamic analysis of warpage risk before actual welding, allowing for timely adjustments to ensure high-quality welding by identifying and mitigating warpage risks, thereby improving the reliability and efficiency of the circuit board production process.
Implementation Method 1
obtaining a shadow moire distribution diagram of the multi-layer circuit board under a grating through a shadow moire technique, and calculating a relative vertical displacement of the multi-layer circuit board during a welding process according to the shadow moire distribution diagram
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A welding quality processing method and device, and a circuit board are provided. The method includes: obtaining warpage data of each circuit board layer in a multi-layer circuit board under a preset welding temperature change curve; performing simulation according to a stacked state of the multi-layer circuit board and the warpage data to generate a warpage level of each region in the multi-layer circuit board in the stacked state; and processing the multi-layer circuit board according to the warpage level.