PCB Wiring Adhesion via Plasma Treatment
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Solution Overview
Problem
In printed circuit boards, the adhesiveness between electroless plating layers and electroplating layers is insufficient, leading to interlayer separation, especially when the width of wiring parts is reduced, which affects the reliability of the circuit board.
Innovation Solution
A printed circuit board with a conductive pattern featuring an electroless plating layer and an electroplating layer stacked on a base film, where the void density at the interface between the layers is minimized through plasma treatment and controlled ashing of the resist pattern, ensuring the layers adhere strongly even at finer pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring parts are arranged at finer pitch to reduce size and weight, then productivity and device miniaturization are improved, but adhesiveness between electroless plating layer and electroplating layer deteriorates, causing interlayer separation
Solution Approach 1:
The patent applies preliminary action by performing plasma treatment on the electroless plating layer surface before electroplating. This preliminary surface activation creates a more reactive surface that enhances subsequent adhesion between layers, preventing interlayer separation even when wiring parts are arranged at finer pitches
Solution Approach 2:
The patent changes physical parameters by controlling plasma treatment conditions (power, gas flow rate, treatment time) to optimize surface activation. By adjusting these parameters, the surface energy and roughness of the electroless plating layer are modified to improve interlayer adhesiveness while maintaining fine wiring pitch
2Length of moving object
If wiring width is reduced to achieve finer pitch, then device miniaturization is improved, but void density at the interface increases, leading to interlayer separation
Solution Approach 1:
The patent replaces conventional thermal drying with plasma treatment to remove moisture and organic substances from the electroless plating layer surface. This substitution of the drying mechanism with plasma-based surface treatment effectively reduces void density at the interface, even when wiring width is reduced to achieve finer pitch
Solution Approach 2:
The patent changes the physical state and surface properties of the electroless plating layer through controlled plasma treatment parameters. By optimizing plasma power, gas composition, and treatment duration, the surface is activated to minimize void formation during subsequent electroplating, maintaining manufacturing precision at reduced wiring dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively suppresses separation between the electroless and electroplating layers, maintaining the integrity of the circuit board even at reduced wiring widths, enhancing the reliability and conductivity of the printed circuit board.
Implementation Method 1
a step of subjecting surfaces of the resist pattern and the electroless plating layer after the resist pattern-forming step to plasma treatment
Implementation Method 2
a step of subjecting the one surface of the base film to electroless plating
Implementation Method 3
a step of subjecting the surface of the electroless plating layer after the plasma treatment step to electroplating
Data Source
AI summary
A printed circuit board according to an embodiment of the present disclosure includes a base film having an insulating property, and a conductive pattern that is stacked on at least one surface of the base film and that includes a plurality of wiring parts arranged in parallel. The plurality of wiring parts have an average width of 5 μm or more and 15 μm or less. The plurality of wiring parts have an electroless plating layer and an electroplating layer stacked on the electroless plating layer. A void density at an interface between the electroless plating layer and the electroplating layer in a section of the plurality of wiring parts in a thickness direction is 0.01 μm2/μm or less.