Parameterized Cell Layout Generation Guided by Design Rule Checking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As process technologies advance, generating optimal layouts for parameterized cells in integrated circuits that satisfy complex design rules becomes challenging due to estimation errors, leading to design rule violations and the need for conservative, less-than-ideal layouts.
Innovation Solution
A systematic approach is introduced where a model with parameters for generating layouts is defined, and initial layouts are generated based on initial parameter values. Design rule checking identifies violations, and reports are used to adjust parameter values iteratively until a 'DRC clean' layout is achieved, utilizing callback functions and property files to manage design rule information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PCell generator uses estimation approach to determine geometry positions and dimensions, then layout generation speed is improved, but manufacturing precision deteriorates due to deviation between estimate and actual numbers
Solution Approach 1:
The patent applies preliminary action by performing design rule checking on the initial layout before finalization. The DRC is executed early in the process to identify potential violations, allowing the system to adjust parameters proactively rather than reactively. This preliminary validation step ensures that the layout meets all design rules while maintaining generation speed.
Solution Approach 2:
The patent implements feedback by using DRC violation reports to iteratively adjust layout parameters. The system generates an initial layout, checks it for DRC violations, and uses the feedback from violation reports to refine parameter values. This closed-loop feedback mechanism continues until the layout is DRC clean, ensuring both speed and precision.
2Reliability
If PCell generator takes conservative approach with larger dimensions and spacing, then reliability is improved by satisfying worst case scenarios, but manufacturing precision deteriorates as layouts become less than ideal
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting layout parameters based on DRC feedback. Instead of using fixed conservative values, the system modifies parameters such as geometry positions, dimensions, and spacing iteratively. The DRC violation reports provide specific guidance on which parameters need adjustment, allowing the system to achieve optimal values rather than relying on conservative estimates.
Solution Approach 2:
The patent implements dynamics by making the layout generation process adaptive and iterative. The system starts with initial parameter estimates and dynamically adjusts them based on DRC results. This dynamic approach allows the layout to evolve from an initial conservative estimate to an optimized final design that satisfies all design rules without unnecessary conservatism.
3Adaptability or versatility
If design rules become more complex with advanced process technologies, then adaptability is improved to handle new requirements, but device complexity increases making it difficult to generate optimal layouts
Solution Approach 1:
The patent introduces an intermediary component - the DRC system - that mediates between the complex design rules and the layout generation process. The DRC acts as a translator that takes complex design rule specifications and converts them into actionable feedback through violation reports. This intermediary simplifies the interaction by providing clear, structured information about what needs to be changed, reducing the complexity burden on the layout generation system.
Solution Approach 2:
The patent applies segmentation by breaking down the complex layout generation process into distinct stages: initial parameter estimation, initial layout generation, DRC checking, violation analysis, and parameter adjustment. Each stage handles a specific aspect of the problem, making the overall complex process more manageable. The DRC violation reports further segment the feedback by identifying specific rules violated and their locations, enabling targeted adjustments.
Data Source
AI summary
A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated.