P-Cell Mirror Caching for EDA Design Cycle Optimization
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Solution Overview
Problem
Existing electronic design automation (EDA) tools face challenges in efficiently utilizing previously designed parameterized cells in new technologies, leading to increased computational overhead and delays due to repeated evaluations of pcell variants during design processes.
Innovation Solution
Implementing a pcell mirror caching system that postpones evaluation from the initial stage to the instance header binding stage, allowing for caching of evaluation results in a central or mirror cache, and synchronizing these caches to reduce the need for repeated evaluations across sessions and libraries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pcell evaluation is performed at the initial stage, then design can be validated early, but computational overhead and design cycle time increase due to repeated evaluations
Solution Approach 1:
The patent performs preliminary evaluation of parameterized cells at the instance header binding stage rather than at the initial design stage. This preliminary action allows the system to pre-compute and cache evaluation results, which are then reused during subsequent design processes, thereby reducing repeated computational overhead while maintaining design validation reliability.
Solution Approach 2:
The patent implements a caching mechanism that creates a mirror copy of the central cache within the design library. This mirror cache stores pre-computed evaluation results of parameterized cells, allowing the system to retrieve cached results instead of performing repeated evaluations. The copying approach significantly reduces computational overhead and design cycle time while maintaining validation accuracy.
2Measurement precision
If repeated evaluations of pcell variants are performed, then design accuracy is maintained, but computational overhead increases
Solution Approach 1:
The patent creates a mirror cache that copies evaluation results from the central cache into the design library. This allows the system to retrieve pre-computed accurate evaluation results without performing repeated computations. The mirror cache mechanism maintains design accuracy by storing and reusing verified evaluation data, thereby significantly reducing computational overhead and energy consumption.
Solution Approach 2:
The patent recovers and reuses previously computed evaluation results through the caching mechanism. Instead of discarding and recomputing evaluation results for parameterized cell variants, the system retrieves cached results that have been verified for accuracy. This approach maintains design accuracy while reducing the computational resources required for repeated evaluations.
3Device complexity
If evaluation results are cached in central cache only, then storage is simplified, but access time and synchronization across sessions are delayed
Solution Approach 1:
The patent segments the central cache into multiple mirror caches distributed within the design library. This segmentation allows different parts of the system to access cached evaluation results from locally stored mirrors rather than from a single centralized location. The segmented architecture reduces access time by enabling parallel retrieval operations while maintaining simplified cache management through synchronization mechanisms.
Solution Approach 2:
The patent introduces mirror caches as intermediary storage locations between the central cache and the design processes. These mirror caches act as mediators that store copies of evaluation results, allowing fast local access without requiring direct interaction with the central cache. The intermediary mirrors reduce access time and enable better synchronization across multiple design sessions.
Data Source
AI summary
In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present.